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BSP430
20141115
Board Support Package for MSP430 microcontrollers
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BSP430
20141115
Board Support Package for MSP430 microcontrollers
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Common header included by all BSP430 leaf headers. More...
#include <msp430.h>#include <stdint.h>#include <stddef.h>#include <stdbool.h>#include "bsp430_config.h"Go to the source code of this file.
Common header included by all BSP430 leaf headers.
This must be included by all BSP430 headers that do not include another BSP430 header, so that it is available in all environments where a BSP430 capability is referenced. It is responsible for including any RTOS-related header files that contain application-specific configuration information that must be consistent between headers and implementation files.
| #define BSP430_CORE_DECLARE_INTERRUPT | ( | iv_ | ) | void __attribute__((__interrupt__(iv_))) |
Mark a function as an interrupt handler.
The technique required varies among toolchains.
| iv_ | the TI header constant identifying the interrupt, e.g USCI_B2_VECTOR |
| #define BSP430_CORE_DELAY_CYCLES | ( | duration_mclk_ | ) | __delay_cycles(duration_mclk_) |
A function macro which requests a delay for a specific number of MCLK cycles.
This macro could be used to abstract between the spelling used by different toolchains for the __delay_cycles() intrinsic, but its primary purpose is to succinctly support watchdog by allowing the loop to be broken or not depending on compile time capabilities.
In most cases, this feature will be invoked with a duration that is far less than BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES, but if not it will function. The duration of the delay will be slightly extended as a result of the machinery supporting the watchdog. For real applications, if you want to delay so long you should probably be using a timer.
| duration_mclk_ | the number of MCLK cycles for which the delay is desired. This must be a compile-time integer constant compatible with unsigned long. configBSP430_CORE_SUPPORT_WATCHDOG is enabled and the constant exceeds BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES, a watchdog clear will be issued after every such period. |
| #define BSP430_CORE_DISABLE_INTERRUPT | ( | ) | __disable_interrupt() |
Clear the status register GIE bit so that interrupts are disabled.
| #define BSP430_CORE_ENABLE_INTERRUPT | ( | ) | __enable_interrupt() |
Set the status register GIE bit so that interrupts are enabled.
nop after the eint when BSP430_CORE_FAMILY_IS_5XX is true, on the assumption that MSP430 erratum CPU42 is present and has not been worked around by the compiler.| #define BSP430_CORE_FAMILY_IS_5XX 0 |
Defined to a value that is true if the build target is an MCU in the 5xx/FR5xx/6xx family. These MCUs have incompatible HPL structures compared with the same peripheral in earlier families; where user or library code must take into account those differences, this flag may be used in a prepropcessor condition to detect the situation.
In the future it may be necessary to distinguish membership in this family from the CPU architecture, but for now the presence of the MSP430_HAS_MSP430XV2_CPU preprocessor symbol in <msp430.h> is what controls the value of this flag.
| #define BSP430_CORE_INLINE __inline__ |
Defined to a true value if the Texas Instruments compiler is being used.
The TI compiler is part of Code Composer Studio, but itself has no clear dependencies on CCS and internally uses a different version series. Since BSP430 has no IDE infrastructure, the toolchain is identified by the compiler (TI), not the IDE (CCS).
Most toolchains support this feature, but the spelling of the request varies.
The toolchain is free to ignore the request, which is after all only the developer's expert opinion. When optimizing for size toolchains are likely to ignore this if more than one call site is in the translation unit.
| #define BSP430_CORE_INLINE_FORCED BSP430_CORE_INLINE __attribute__((__always_inline__)) |
Insist that a function be inlined.
Use this when BSP430_CORE_INLINE is being ignored. Not all toolchains will support this; on those it should be treated as BSP430_CORE_INLINE.
| #define BSP430_CORE_INTERRUPT_STATE_T __istate_t |
A type that can be used to declare a variable that will hold interrupt state stored by BSP430_CORE_SAVE_INTERRUPT_STATE.
| #define BSP430_CORE_LPM_ENTER | ( | lpm_bits_ | ) | __bis_status_register(BSP430_CORE_LPM_SR_MASK & (lpm_bits_)) |
Enter a low-power mode
This sets the status register bits in accordance to the bits specified in lpm_bits_.
This macro is normally intended to be invoked when interrupts are enabled. It does not add GIE to lpm_bits. If invoked when interrupts are disabled and GIE is not in lpm_bits it is unlikely to ever return.
Interrupts normally remain enabled after BSP430_CORE_LPM_ENTER() completes.
| lpm_bits_ | bits to be set in the status register. The value is masked by BSP430_CORE_LPM_SR_MASK before being written. |
| #define BSP430_CORE_LPM_ENTER_NI | ( | lpm_bits_ | ) | BSP430_CORE_LPM_ENTER(GIE | (lpm_bits_)) |
Enter a low-power mode while interrupts are disabled
This invokes BSP430_CORE_LPM_ENTER(lpm_bits | GIE). It exists to explicitly note that entering LPM when interrupts are disabled should normally set GIE so that the application can be woken.
Interrupts normally remain enabled after BSP430_CORE_LPM_ENTER_NI() completes. Using BSP430_CORE_DISABLE_INTERRUPT() immediately after BSP430_CORE_LPM_ENTER_NI() will disable interrupts again, though there is a window where additional interrupts may be processed before this can happen.
| lpm_bits_ | as with BSP430_CORE_LPM_ENTER() |
| #define BSP430_CORE_LPM_EXIT_FROM_ISR | ( | lpm_bits_ | ) | __bic_status_register_on_exit(BSP430_CORE_LPM_SR_MASK & (lpm_bits_)) |
Exit low-power mode on return from ISR
This clears the status register bits provided in lpm_bits from the saved status register value stored in the stack by the interrupt invocation, so that when the interrupt returns the change will take effect.
| lpm_bits_ | bits to be cleared in the stored status register. The value is masked by BSP430_CORE_LPM_SR_MASK before being written. |
The bits cleared in the stored status word to exit from low power mode in an interrupt.
This starts as either LPM4_bits or (LPM4_bits & ~SCG0), depending on configBSP430_CORE_DISABLE_FLL. GIE is added if configBSP430_CORE_LPM_EXIT_CLEAR_GIE is true.
| #define BSP430_CORE_LPM_LPMXp5 0x0100 |
Bit indicating that LPMx.5 should be entered.
Where an integer value represents a low power mode configuration, this bit may be set along with LPM3_bits or LPM4_bits to specify that the LPMx.5 mode feature supported by the Power Management Module should also apply.
Bitmask isolating LPM-related bits recorded in status register.
These are SCG1, SCG0, OSCOFF, CPUOFF, and (just in case) GIE. Other bits are eliminated from any LPM bit value before mutating a status register setting in either BSP430_CORE_LPM_ENTER() or BSP430_CORE_LPM_EXIT_FROM_ISR().
| #define BSP430_CORE_MS_TO_TICKS | ( | ms_, | |
| hz_ | |||
| ) | (((ms_) * (unsigned long)(hz_)) / 1000UL) |
Generic convert from milliseconds to ticks at some frequency.
unsigned long and ms_. The fastest code is generated when parameters are compile-time constants.ms_ or hz_ is large, it may be necessary to cast ms_ to unsigned long long to avoid integer overflow.| #define BSP430_CORE_NDEBUG 0 |
Include runtime checks for critical errors.
There may be situations where BSP430 can add checks that decrease performance but detect situations that would otherwise lead to very hard to diagnose bugs. Like the classic NDEBUG macro used for assert this macro may be defined to a true value to disable such checks.
This is used only in performance-critical code where a check provides safety for a situation that otherwise would be extremely difficult to diagnose.
Seriously, you don't ever want to set this.
| #define BSP430_CORE_PACKED_STRUCT | ( | nm_ | ) | struct __attribute__((__packed__)) nm_ |
Declare a packed structure in a toolchain-specific manner.
| nm_ | name of the structure to be declared |
This expands to struct nm_ annotated with toolchain-specific directives to ensure the structure contents have no padding. It is used for binary messages that mix types which might normally require padding to maintain MCU-standard alignment.
| #define BSP430_CORE_RESTORE_INTERRUPT_STATE | ( | state_ | ) |
A function macro that will enable or disable interrupts as recorded in the provided state parameter. The parameter value should have been created using BSP430_CORE_SAVE_INTERRUPT_STATE.
| state_ | where the interrupt enable/disable state is stored. |
| #define BSP430_CORE_SAVE_INTERRUPT_STATE | ( | state_ | ) |
A function macro that will record whether interrupts are currently enabled in the state parameter. The parameter should subsequently be passed to BSP430_CORE_RESTORE_INTERRUPT_STATE.
The canonical code sequence for this is:
| state_ | where the interrupt enable/disable state is stored. |
| #define BSP430_CORE_SAVED_INTERRUPT_STATE | ( | var_ | ) | BSP430_CORE_INTERRUPT_STATE_T var_ = __get_interrupt_state() |
Declare a variable holding interrupt state and initialize it with current state.
This macro supports a simpler canonical sequence:
This approach results from the experience that in a large number of cases the declaration of the variable into which the state is stored is immediately followed by the command that stores the current state into that variable.
| var_ | where the interrupt enable/disable state is stored. |
| #define BSP430_CORE_SWAP_16 | ( | w_ | ) |
Utility to convert a 16-bit word between big-endian and little-endian.
Some toolchains may provide an intrinsic that is faster than basic C code.
| #define BSP430_CORE_SWAP_32 | ( | lw_ | ) |
Utility to convert a 32-bit word between big-endian and little-endian.
Some toolchains may provide an intrinsic that is faster than basic C code.
| #define BSP430_CORE_TICKS_TO_MS | ( | ticks_, | |
| hz_ | |||
| ) | ((1000UL * (ticks_)) / (hz_)) |
Generic convert from ticks at some frequency to milliseconds.
unsigned long and ticks_. The fastest code is generated when parameters are compile-time constants.ticks_ is large, it may be necessary to cast it to unsigned long long to avoid integer overflow.| #define BSP430_CORE_TICKS_TO_US | ( | ticks_, | |
| hz_ | |||
| ) | ((1000000UL * (ticks_)) / (hz_)) |
Generic convert from ticks at some frequency to microseconds.
unsigned long and ticks_. The fastest code is generated when parameters are compile-time constants.ticks_ is more than 2000 it may be necessary to cast it to unsigned long long to avoid integer overflow.| #define BSP430_CORE_TOOLCHAIN_GCC (1 < __GNUC__) |
Defined to a true value if GCC is being used
| #define BSP430_CORE_TOOLCHAIN_GCC_MSP430_ELF (BSP430_CORE_TOOLCHAIN_GCC && ! BSP430_CORE_TOOLCHAIN_GCC_MSPGCC) |
Defined to a true value if msp430-elf GCC is being used
| #define BSP430_CORE_TOOLCHAIN_GCC_MSPGCC (1 < __MSPGCC__) |
Defined to a true value if mspgcc is being used
| #define BSP430_CORE_TOOLCHAIN_LIBC_MSP430_LIBC BSP430_CORE_TOOLCHAIN_GCC_MSPGCC |
Defined to a true value iff the stdc library is msp430-libc
Technically this should use MSP430_LIBC which will be obtained implicitly from <msp430libc.h> via some other include file, but in practice we have no guarantee it'll be included so we'll treat use of the mspgcc toolchain as the indicator.
| #define BSP430_CORE_TOOLCHAIN_LIBC_NEWLIB BSP430_CORE_TOOLCHAIN_GCC_MSP430_ELF |
Defined to a true value iff the stdc library is newlib.
<newlib.h> defines _NEWLIB_VERSION, and is included by <_ansi.h> which is included by most standard headers, but not any of the ones included by this file. Treat use of msp430-elf toolchain as the indicator.
| #define BSP430_CORE_US_TO_TICKS | ( | us_, | |
| hz_ | |||
| ) | (((us_) * (unsigned long)(hz_)) / 1000000UL) |
Generic convert from microseconds to ticks at some frequency.
unsigned long and us_. The fastest code is generated when parameters are compile-time constants.us_ or hz_ is large, it may be necessary to cast us_ to unsigned long long to avoid integer overflow.| #define BSP430_CORE_WATCHDOG_CLEAR | ( | ) | do { } while (0) |
A function macro which should expand to a toolchain-specific statement that resets ("kicks") the watchdog timer.
Be aware that the toolchain may provide an intrinsic with special semantics, which should be understood before using its definition. For example, in MSPGCC the __watchdog_clear() intrinsic references a clear value managed with __set_watchdog_clear_value(). Invoking __watchdog_clear() after manually halting the watchdog will restart it in its last active configuration.
It is safe to use this macro regardless of whether configBSP430_CORE_SUPPORT_WATCHDOG is true. When the watchdog is not supported, it evalutes to an empty statement.
| #define BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES 10000U |
The maximum number of delay cycles that can be executed without obliging BSP430 to execute BSP430_CORE_WATCHDOG_CLEAR().
If you know that <bsp430/clock.h> is available, you could define this in terms of BSP430_CLOCK_NOMINAL_MCLK_HZ.
| #define BSP430_PERIPH_CPPID_EUSCI_A0 31 |
Constant to identify BSP430_PERIPH_EUSCI_A0 in preprocessor checks
| #define BSP430_PERIPH_CPPID_EUSCI_A1 32 |
Constant to identify BSP430_PERIPH_EUSCI_A1 in preprocessor checks
| #define BSP430_PERIPH_CPPID_EUSCI_A2 33 |
Constant to identify BSP430_PERIPH_EUSCI_A2 in preprocessor checks
| #define BSP430_PERIPH_CPPID_EUSCI_B0 34 |
Constant to identify BSP430_PERIPH_EUSCI_B0 in preprocessor checks
| #define BSP430_PERIPH_CPPID_NONE 0 |
Constant to specify no peripheral in preprocessor checks.
Where a functional resource may be specified by either an application or a platform, we need a way to identify it that permits preprocessor checks that default the corresponding core resource capability. The peripheral handle values such as BSP430_PERIPH_TB0 cannot be used for this, since their expansion includes cast operations that cannot be used in preprocessor expressions. Consequently there is a parallel integral-valued C pre-processor identifier for each MCU peripheral.
For example, if BSP430_UPTIME_TIMER_PERIPH_CPPID is defined to BSP430_PERIPH_CPPID_TB0, then the following code ensures that configBSP430_HAL_TB0 and configBSP430_HAL_TB0_ISR are both defined to 1.
See <bsp430/periph/want_.h> for an infrastructure that uses these constants to enable features without complex preprocessor manipulation within user code.
The value for BSP430_PERIPH_CPPID_NONE indicates that no core resource is associated with the functional resource.
| #define BSP430_PERIPH_CPPID_PORT1 1 |
Constant to identify BSP430_PERIPH_PORT1 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT10 10 |
Constant to identify BSP430_PERIPH_PORT10 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT11 11 |
Constant to identify BSP430_PERIPH_PORT11 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT2 2 |
Constant to identify BSP430_PERIPH_PORT2 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT3 3 |
Constant to identify BSP430_PERIPH_PORT3 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT4 4 |
Constant to identify BSP430_PERIPH_PORT4 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT5 5 |
Constant to identify BSP430_PERIPH_PORT5 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT6 6 |
Constant to identify BSP430_PERIPH_PORT6 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT7 7 |
Constant to identify BSP430_PERIPH_PORT7 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT8 8 |
Constant to identify BSP430_PERIPH_PORT8 in preprocessor checks
| #define BSP430_PERIPH_CPPID_PORT9 9 |
Constant to identify BSP430_PERIPH_PORT9 in preprocessor checks
| #define BSP430_PERIPH_CPPID_TA0 12 |
Constant to identify BSP430_PERIPH_TA0 in preprocessor checks
| #define BSP430_PERIPH_CPPID_TA1 13 |
Constant to identify BSP430_PERIPH_TA1 in preprocessor checks
| #define BSP430_PERIPH_CPPID_TA2 14 |
Constant to identify BSP430_PERIPH_TA2 in preprocessor checks
| #define BSP430_PERIPH_CPPID_TA3 15 |
Constant to identify BSP430_PERIPH_TA3 in preprocessor checks
| #define BSP430_PERIPH_CPPID_TB0 16 |
Constant to identify BSP430_PERIPH_TB0 in preprocessor checks
| #define BSP430_PERIPH_CPPID_TB1 17 |
Constant to identify BSP430_PERIPH_TB1 in preprocessor checks
| #define BSP430_PERIPH_CPPID_TB2 18 |
Constant to identify BSP430_PERIPH_TB2 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI5_A0 23 |
Constant to identify BSP430_PERIPH_USCI5_A0 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI5_A1 24 |
Constant to identify BSP430_PERIPH_USCI5_A1 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI5_A2 25 |
Constant to identify BSP430_PERIPH_USCI5_A2 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI5_A3 26 |
Constant to identify BSP430_PERIPH_USCI5_A3 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI5_B0 27 |
Constant to identify BSP430_PERIPH_USCI5_B0 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI5_B1 28 |
Constant to identify BSP430_PERIPH_USCI5_B1 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI5_B2 29 |
Constant to identify BSP430_PERIPH_USCI5_B2 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI5_B3 30 |
Constant to identify BSP430_PERIPH_USCI5_B3 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI_A0 19 |
Constant to identify BSP430_PERIPH_USCI_A0 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI_A1 20 |
Constant to identify BSP430_PERIPH_USCI_A1 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI_B0 21 |
Constant to identify BSP430_PERIPH_USCI_B0 in preprocessor checks
| #define BSP430_PERIPH_CPPID_USCI_B1 22 |
Constant to identify BSP430_PERIPH_USCI_B1 in preprocessor checks
| #define BSP430_RTOS_YIELD_FROM_ISR | ( | ) | do { } while (0) |
Instruct the RTOS environment to execute a context switch. This should only be invoked from with the function that is the top-half of an interrupt service routine, and is usually invoked within BSP430_HAL_ISR_CALLBACK_TAIL_NI when BSP430_HAL_ISR_CALLBACK_YIELD has been set.
It is defined to a no-op in environments that do not support context switches.
| #define BSP430_VERSION 20141115 |
Version identifier for the BSP430 library
A monotonically non-decreasing integer reflecting the version of the BSP430 library that is being used. The value represents a development freeze date in the form YYYYMMDD as a decimal number.
| #define configBSP430_CORE_DISABLE_FLL (defined(__MSP430_HAS_UCS__) || defined(__MSP430_HAS_UCS_RF__)) |
This macro may be defined to a true value to request that SCG0 be set after vBSP430platformInitialize_ni() configures the clocks, preventing the FLL from changing the DCO configuration without application intervention. It also enables steps to prevent SCG0 from being cleared in other situations, such as leaving low-power mode.
The UCS peripheral has several errata which result in severe clock instabilities when the FLL is allowed to run unmanaged. These include UCS7 ("DCO drifts when servicing short ISRs when in LPM0 or exiting active from ISRs for short periods of time" and UCS10 ("Modulation causes shift in DCO frequency"). The latter is documented in UCS10 Guidance. The UCS implementation of iBSP430ucsTrimDCOCLKDIV_ni() supports the UCS10 workaround.
Because of the severe impact of UCS7 and UCS10, this flag is enabled by default on any platform that uses the UCS peripheral and is not known to have the erratum fixed. It is made generic in case there are other cases where SCG0 should left set throughout application execution.
| #define configBSP430_CORE_INCLUDE_BSP430_CONFIG_FILE 1 |
BSP430 depends heavily on configuration specified by preprocessor tokens defined to true or false values. Proper application behavior requires that all object files be built using the same configuration settings.
All BSP430 implementation files include <bsp430/core.h>, either directly or through other headers. Defining configBSP430_CORE_INCLUDE_BSP430_CONFIG_FILE to a true value (which is its default) will cause this header to include a file named "bsp430_config.h", which is presumed to be in the compiler's include path. All application configuration may be placed into this file. It is recommended that this file end with the inclusion of <bsp430/platform/bsp430_config.h> to reduce the amount of generic configuration that must be supplied.
If you provide configuration solely through external means (e.g., through -D arguments to the preprocessor) you can inhibit this inclusion by defining configBSP430_CORE_INCLUDE_BSP430_CONFIG_FILE to 0.
| #define configBSP430_CORE_LPM_EXIT_CLEAR_GIE 0 |
Define to true to have BSP430 ISRs clear GIE when exiting LPM.
GIE must be set in the status register for maskable interrupts to be processed. In special cases applications may wish to have GIE cleared by interrupt handlers, so when control returns to the program the effects of already-handled interrupts can be processed before any new interrupts are handled.
When this macro is defined to a true value, GIE is added to BSP430_CORE_LPM_EXIT_MASK, meaning that it will be cleared along with LPM bits when BSP430_HAL_ISR_CALLBACK_EXIT_LPM is specified in the return value of an interrupt callback.
| #define configBSP430_CORE_SUPPORT_WATCHDOG 0 |
Control use of the watchdog infrastructure by BSP430.
If defined to a true value, the function macros BSP430_CORE_WATCHDOG_CLEAR() and BSP430_CORE_DELAY_CYCLES() will reset the watchdog in accordance with their descriptions. If false, those macros will not manipulate the watchdog register.
When watchdog support is enabled, all BSP430 functions that might execute for more than 30 milliseconds with an MCLK frequency of at least 1 MHz will invoke BSP430_CORE_WATCHDOG_CLEAR() at a frequency of at least once every 30 milliseconds.
See BSP430_PLATFORM_BOOT_DISABLE_WATCHDOG, which defaults to true if and only if configBSP430_CORE_SUPPORT_WATCHDOG is false.
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