Stripped <msp430.h> header supporting Doxygen links. More...

Macros
#define	BIT0 (0x0001)

#define	BIT1 (0x0002)

#define	BIT2 (0x0004)

#define	BIT3 (0x0008)

#define	BIT4 (0x0010)

#define	BIT5 (0x0020)

#define	BIT6 (0x0040)

#define	BIT7 (0x0080)

#define	BIT8 (0x0100)

#define	BIT9 (0x0200)

#define	BITA (0x0400)

#define	BITB (0x0800)

#define	BITC (0x1000)

#define	BITD (0x2000)

#define	BITE (0x4000)

#define	BITF (0x8000)

#define	C (0x0001)

#define	Z (0x0002)

#define	N (0x0004)

#define	V (0x0100)

#define	GIE (0x0008)

#define	CPUOFF (0x0010)

#define	OSCOFF (0x0020)

#define	SCG0 (0x0040)

#define	SCG1 (0x0080)

#define	LPM0_bits (CPUOFF)

#define	LPM1_bits (SCG0\|CPUOFF)

#define	LPM2_bits (SCG1\|CPUOFF)

#define	LPM3_bits (SCG1\|SCG0\|CPUOFF)

#define	LPM4_bits (SCG1\|SCG0\|OSCOFF\|CPUOFF)

#define	__MSP430_HAS_MSP430XV2_CPU__

#define	MC_0 (0x0000)

#define	MC_1 (0x0010)

#define	MC_2 (0x0020)

#define	MC_3 (0x0030)

#define	ID_0 (0x0000)

#define	ID_1 (0x0040)

#define	ID_2 (0x0080)

#define	ID_3 (0x00C0)

#define	CCIS_0 (0x0000)

#define	CCIS_1 (0x1000)

#define	CCIS_2 (0x2000)

#define	CCIS_3 (0x3000)

#define	CM_0 (0x0000)

#define	CM_1 (0x4000)

#define	CM_2 (0x8000)

#define	CM_3 (0xC000)

#define	CM1 (0x8000)

#define	CM0 (0x4000)

#define	CCIS1 (0x2000)

#define	CCIS0 (0x1000)

#define	SCS (0x0800)

#define	SCCI (0x0400)

#define	CAP (0x0100)

#define	OUTMOD2 (0x0080)

#define	OUTMOD1 (0x0040)

#define	OUTMOD0 (0x0020)

#define	CCIE (0x0010)

#define	CCI (0x0008)

#define	OUT (0x0004)

#define	COV (0x0002)

#define	CCIFG (0x0001)

#define	SCS (0x0800)

#define	SCCI (0x0400)

#define	CAP (0x0100)

#define	SELA_0 (0x0000)

#define	SELA_1 (0x0100)

#define	SELA_2 (0x0200)

#define	SELA_3 (0x0300)

#define	SELA_4 (0x0400)

#define	SELA_5 (0x0500)

#define	SELA_6 (0x0600)

#define	SELA_7 (0x0700)

#define	LFXT1S_0 (0x00)

#define	LFXT1S_1 (0x10)

#define	LFXT1S_2 (0x20)

#define	LFXT1S_3 (0x30)

#define	UCBUSY (0x01)

#define	UCPEN (0x80)

#define	UCCKPH (0x80)

#define	UCA10 (0x80)

#define	UCPAR (0x40)

#define	UCCKPL (0x40)

#define	UCSLA10 (0x40)

#define	UCMSB (0x20)

#define	UCMM (0x20)

#define	UC7BIT (0x10)

#define	UCSPB (0x08)

#define	UCMST (0x08)

#define	UCSYNC (0x01)

#define	UCMODE_0 (0x00)

#define	UCMODE_1 (0x02)

#define	UCMODE_2 (0x04)

#define	UCMODE_3 (0x06)

#define	UCRXEIE (0x20)

#define	UCBRKIE (0x10)

#define	UCTR (0x10)

#define	UCDORM (0x08)

#define	UCTXNACK (0x08)

#define	UCTXADDR (0x04)

#define	UCTXSTP (0x04)

#define	UCTXBRK (0x02)

#define	UCTXSTT (0x02)

#define	UCSWRST (0x01)

#define	UCSSEL_0 (0x00)

#define	UCSSEL_1 (0x40)

#define	UCSSEL_2 (0x80)

#define	UCSSEL_3 (0xC0)

#define	PMMCOREV_0 (0x0000)

#define	PMMCOREV_1 (0x0001)

#define	PMMCOREV_2 (0x0002)

#define	PMMCOREV_3 (0x0003)

#define	LOCKLPM5 (0x0001)

#define	SVSMHRRL1 (0x0002)

#define	SVSMHRRL2 (0x0004)

#define	SVSMHDLYST (0x0008)

#define	SVSHMD (0x0010)

#define	SVSMHEVM (0x0040)

#define	SVSMHACE (0x0080)

#define	SVSHRVL0 (0x0100)

#define	SVSHRVL1 (0x0200)

#define	SVSHE (0x0400)

#define	SVSHFP (0x0800)

#define	SVMHOVPE (0x1000)

#define	SVMHE (0x4000)

#define	SVMHFP (0x8000)

#define	SVSMLRRL0 (0x0001)

#define	SVSMLRRL1 (0x0002)

#define	SVSMLRRL2 (0x0004)

#define	SVSMLDLYST (0x0008)

#define	SVSLMD (0x0010)

#define	SVSMLEVM (0x0040)

#define	SVSMLACE (0x0080)

#define	SVSLRVL0 (0x0100)

#define	SVSLRVL1 (0x0200)

#define	SVSLE (0x0400)

#define	SVSLFP (0x0800)

#define	SVMLOVPE (0x1000)

#define	SVMLE (0x4000)

#define	SVMLFP (0x8000)

#define	TLV_START (0x1A08)

#define	TLV_END (0x1AFF)

#define	TLV_LDTAG (0x01)

#define	TLV_PDTAG (0x02)

#define	TLV_BLANK (0x05)

#define	TLV_DIERECORD (0x08)

#define	TLV_ADCCAL (0x11)

#define	TLV_ADC12CAL (0x11)

#define	TLV_ADC10CAL (0x13)

#define	TLV_REFCAL (0x12)

#define	TLV_TAGEXT (0xFE)

#define	TAG_DCO_30 (0x01)

#define	TAG_ADC10_1 (0x08)

#define	TAG_ADC12_1 (0x08)

#define	TAG_EMPTY (0xFE)

#define	LOCKA (0x0040)

#define	LOCKINFO (0x0080)

#define	SYSRSTIV_BOR (0x0002)

#define	SYSRSTIV_RSTNMI (0x0004)

#define	SYSRSTIV_SVMBOR (0x0004)

#define	SYSRSTIV_DOBOR (0x0006)

#define	SYSRSTIV_RSTNMI (0x0006)

#define	SYSRSTIV_DOBOR (0x0008)

#define	SYSRSTIV_LPM5WU (0x0008)

#define	SYSRSTIV_SECYV (0x000A)

#define	SYSRSTIV_DOPOR (0x000C)

#define	SYSRSTIV_SVSL (0x000C)

#define	SYSRSTIV_SVSLIFG (0x000C)

#define	SYSRSTIV_SVSH (0x000E)

#define	SYSRSTIV_SVSHIFG (0x000E)

#define	SYSRSTIV_WDTTO (0x000E)

#define	SYSRSTIV_SVML_OVP (0x0010)

#define	SYSRSTIV_WDTKEY (0x0010)

#define	SYSRSTIV_CCSKEY (0x0012)

#define	SYSRSTIV_SVMH_OVP (0x0012)

#define	SYSRSTIV_DOPOR (0x0014)

#define	SYSRSTIV_PMMKEY (0x0014)

#define	SYSRSTIV_WDTTO (0x0016)

#define	SYSRSTIV_PERF (0x0016)

#define	SYSRSTIV_WDTKEY (0x0018)

#define	SYSRSTIV_FRCTLPW (0x001A)

#define	SYSRSTIV_KEYV (0x001A)

#define	SYSRSTIV_FLLUL (0x001C)

#define	SYSRSTIV_DBDIFG (0x001C)

#define	SYSRSTIV_UBDIFG (0x001C)

#define	SYSRSTIV_PLLUL (0x001C)

#define	SYSRSTIV_PERF (0x001E)

#define	SYSRSTIV_PSSKEY (0x0020)

#define	SYSRSTIV_PMMPW (0x0020)

#define	SYSRSTIV_PMMKEY (0x0020)

#define	SYSRSTIV_MPUPW (0x0022)

#define	SYSRSTIV_MPUKEY (0x0022)

#define	SYSRSTIV_CSPW (0x0024)

#define	SYSRSTIV_CSKEY (0x0024)

#define	SYSRSTIV_MPUSEGIIFG (0x0026)

#define	SYSRSTIV_MPUSEGPIFG (0x0026)

#define	SYSRSTIV_MPUSEG1IFG (0x0028)

#define	SYSRSTIV_MPUSEG2IFG (0x002A)

#define	SYSRSTIV_MPUSEG3IFG (0x002C)

#define	SELREF_0 (0x0000)

#define	SELREF_1 (0x0010)

#define	SELREF_2 (0x0020)

#define	SELREF_3 (0x0030)

#define	SELREF_4 (0x0040)

#define	SELREF_5 (0x0050)

#define	SELREF_6 (0x0060)

#define	SELREF_7 (0x0070)

#define	SELREF__XT1CLK (0x0000)

#define	SELREF__REFOCLK (0x0020)

#define	SELREF__XT2CLK (0x0050)

#define	XCAP_0 (0x00)

#define	XCAP_1 (0x04)

#define	XCAP_2 (0x08)

#define	XCAP_3 (0x0C)

#define	XCAP0PF (0x00)

#define	XCAP10PF (0x10)

#define	XCAP14PF (0x20)

#define	XCAP18PF (0x30)

Variables
unsigned int	SVSMHCTL

unsigned int	SVSMLCTL

Detailed Description

Stripped <msp430.h> header supporting Doxygen links.

This file is a fake <msp430.h> header modified so that constants defined by the header are documented for reference from BSP430 documentation. You do not include this one; you include <msp430.h> and the compilation environment resolves this to the one appropriate for your target MCU based on toolchain-specific configuration. For mspgcc, that is the -mmcu= target option.

Documentation text is taken from the <msp430xgeneric.h> header provided in the msp430mcu package at version 20120716, or from the MSP430 5xx/6xx Family Users Guide. The set of peripherals identified as available modules in this example header is both incomplete and generic: not all identified peripherals can be found in an MSP430 MCU.

Warning: Do not assume the values in this documentation are correct. The value for your MCU may be different, but the documentation will still apply.

Homepage: http://github.com/pabigot/bsp430

Macro Definition Documentation

#define __MSP430_HAS_MSP430XV2_CPU__

Definition to show that MCU has MSP430XV2 CPU

This is the defining characteristic for 5xx/6xx family devices (including FR5xx devices).

#define BIT0 (0x0001)

Constant for bit 0 (=least significant bit)

Examples:: rf/cc3000/cli/main.c.

#define BIT1 (0x0002)

Constant for bit 1 (bit 0 is least significant bit)

Examples:: rf/cc3000/cli/main.c.

#define BIT2 (0x0004)

Constant for bit 2 (bit 0 is least significant bit)

Examples:: rf/cc3000/cli/main.c.

#define BIT3 (0x0008)

Constant for bit 3 (bit 0 is least significant bit)

#define BIT4 (0x0010)

Constant for bit 4 (bit 0 is least significant bit)

#define BIT5 (0x0020)

Constant for bit 5 (bit 0 is least significant bit)

#define BIT6 (0x0040)

Constant for bit 6 (bit 0 is least significant bit)

#define BIT7 (0x0080)

Constant for bit 7 (bit 0 is least significant bit)

#define BIT8 (0x0100)

Constant for bit 8 (bit 0 is least significant bit)

#define BIT9 (0x0200)

Constant for bit 9 (bit 0 is least significant bit)

#define BITA (0x0400)

Constant for bit 10 (bit 0 is least significant bit)

#define BITB (0x0800)

Constant for bit 11 (bit 0 is least significant bit)

#define BITC (0x1000)

Constant for bit 12 (bit 0 is least significant bit)

#define BITD (0x2000)

Constant for bit 13 (bit 0 is least significant bit)

#define BITE (0x4000)

Constant for bit 14 (bit 0 is least significant bit)

#define BITF (0x8000)

Constant for bit 15 (bit 0 is least significant bit)

#define C (0x0001)

Carry. This bit is set when the result of an operation produced a carry and cleared when no carry occurred.

#define CAP (0x0100)

Capture mode: 1 /Compare mode : 0

#define CAP (0x0100)

Capture mode: 1 /Compare mode : 0

#define CCI (0x0008)

Capture input signal (read)

#define CCIE (0x0010)

Capture/compare interrupt enable

Examples:: sensors/hh10d/main.c.

#define CCIFG (0x0001)

Capture/compare interrupt flag

Examples:: sensors/hh10d/main.c.

#define CCIS0 (0x1000)

Capture input select 0

#define CCIS1 (0x2000)

Capture input select 1

#define CCIS_0 (0x0000)

Capture input select: 0 - CCIxA

#define CCIS_1 (0x1000)

Capture input select: 1 - CCIxB

#define CCIS_2 (0x2000)

Capture input select: 2 - GND

#define CCIS_3 (0x3000)

Capture input select: 3 - Vcc

#define CM0 (0x4000)

Capture mode 0

#define CM1 (0x8000)

Capture mode 1

#define CM_0 (0x0000)

Capture mode: 0 - disabled

#define CM_1 (0x4000)

Capture mode: 1 - pos. edge

#define CM_2 (0x8000)

Capture mode: 1 - neg. edge

Examples:: bootstrap/clocks/main.c.

#define CM_3 (0xC000)

Capture mode: 1 - both edges

#define COV (0x0002)

Capture/compare overflow flag

#define CPUOFF (0x0010)

CPU off. This bit, when set, turns off the CPU.

#define GIE (0x0008)

General interrupt enable. This bit, when set, enables maskable interrupts. When reset, all maskable interrupts are disabled.

#define ID_0 (0x0000)

Timer input divider: 0 - /1

#define ID_1 (0x0040)

Timer input divider: 1 - /2

#define ID_2 (0x0080)

Timer input divider: 2 - /4

#define ID_3 (0x00C0)

Timer input divider: 3 - /8

#define LFXT1S_0 (0x00)

Mode 0 for LFXT1 : Normal operation (32 KiHz watch)

#define LFXT1S_1 (0x10)

Mode 1 for LFXT1 : Reserved

#define LFXT1S_2 (0x20)

Mode 2 for LFXT1 : VLO

#define LFXT1S_3 (0x30)

Mode 3 for LFXT1 : Digital input signal

#define LOCKA (0x0040)

Segment A Lock bit: read = 1 - Segment is locked (read only)

#define LOCKINFO (0x0080)

Lock INFO Memory bit: read = 1 - Segment is locked (read only)

#define LOCKLPM5 (0x0001)

Lock I/O pin configuration upon entry/exit to/from LPM5

#define LPM0_bits (CPUOFF)

Bits set in status register to enter LPM0

Examples:: bootstrap/applpm/main.c, bootstrap/button/main.c, bootstrap/lpm/main.c, sensors/venus6pps/main.c, and utility/cli/main.c.

#define LPM1_bits (SCG0|CPUOFF)

Bits set in status register to enter LPM1

Examples:: bootstrap/applpm/main.c, bootstrap/lpm/main.c, and sensors/hh10d/main.c.

#define LPM2_bits (SCG1|CPUOFF)

Bits set in status register to enter LPM2

Examples:: bootstrap/applpm/main.c, bootstrap/lpm/main.c, periph/timer/alarm/main.c, and rf/cc3000/cli/main.c.

#define LPM3_bits (SCG1|SCG0|CPUOFF)

Bits set in status register to enter LPM3

Examples:: bootstrap/applpm/main.c, bootstrap/lpm/main.c, rf/cc110x/main.c, and sensors/ds18b20/main.c.

#define LPM4_bits (SCG1|SCG0|OSCOFF|CPUOFF)

Bits set in status register to enter LPM4

Examples:: bootstrap/applpm/main.c, and bootstrap/lpm/main.c.

#define MC_0 (0x0000)

Timer mode control: 0 - Stop

#define MC_1 (0x0010)

Timer mode control: 1 - Up to CCR0

#define MC_2 (0x0020)

Timer mode control: 2 - Continuous up

Examples:: bootstrap/clocks/main.c, periph/timer/alarm/main.c, and sensors/hh10d/main.c.

#define MC_3 (0x0030)

Timer mode control: 3 - Up/Down

#define N (0x0004)

Negative. This bit is set when the result of an operation is negative and cleared when the result is positive.

#define OSCOFF (0x0020)

Oscillator off. This bit, when set, turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or SMCLK.

#define OUT (0x0004)

PWM Output signal if output mode 0

#define OUTMOD0 (0x0020)

Output mode 0

#define OUTMOD1 (0x0040)

Output mode 1

#define OUTMOD2 (0x0080)

Output mode 2

#define PMMCOREV_0 (0x0000)

PMM Core Voltage 0 (1.35V)

Examples:: bootstrap/applpm/main.c.

#define PMMCOREV_1 (0x0001)

PMM Core Voltage 1 (1.55V)

#define PMMCOREV_2 (0x0002)

PMM Core Voltage 2 (1.75V)

#define PMMCOREV_3 (0x0003)

PMM Core Voltage 3 (1.85V)

Examples:: bootstrap/applpm/main.c, and platform/exp430f5529/fatfs/main.c.

#define SCCI (0x0400)

Latched capture signal (read)

#define SCCI (0x0400)

Latched capture signal (read)

#define SCG0 (0x0040)

System clock generator 0. This bit may be used to enable/disable functions in the clock system depending on the device family; for example, FLL disable/enable.

#define SCG1 (0x0080)

System clock generator 1. This bit may be to enable/disable functions in the clock system depending on the device family; for example, DCO bias enable/disable.

#define SCS (0x0800)

Capture sychronize

#define SCS (0x0800)

Capture sychronize

#define SELA_0 (0x0000)

ACLK Source Select 0 (XT1CLK)

#define SELA_1 (0x0100)

ACLK Source Select 1 (VLOCLK)

#define SELA_2 (0x0200)

ACLK Source Select 2 (REFOCLK?)

#define SELA_3 (0x0300)

ACLK Source Select 3 (DCOCLK)

#define SELA_4 (0x0400)

ACLK Source Select 4 (DCOCLKDIV?)

#define SELA_5 (0x0500)

ACLK Source Select 5 (XT2CLK?)

#define SELA_6 (0x0600)

ACLK Source Select 6

#define SELA_7 (0x0700)

ACLK Source Select 7

#define SELREF_0 (0x0000)

UCS : FLL Reference Clock Select 0

#define SELREF_1 (0x0010)

UCS : FLL Reference Clock Select 1

#define SELREF_2 (0x0020)

UCS : FLL Reference Clock Select 2

#define SELREF_3 (0x0030)

UCS : FLL Reference Clock Select 3

#define SELREF_4 (0x0040)

UCS : FLL Reference Clock Select 4

#define SELREF_5 (0x0050)

UCS : FLL Reference Clock Select 5

#define SELREF_6 (0x0060)

UCS : FLL Reference Clock Select 6

#define SELREF_7 (0x0070)

UCS : FLL Reference Clock Select 7

#define SELREF__REFOCLK (0x0020)

UCS : Multiply Selected Loop Freq. By REFOCLK

Examples:: bootstrap/clocks/main.c.

#define SELREF__XT1CLK (0x0000)

UCS : Multiply Selected Loop Freq. By XT1CLK

#define SELREF__XT2CLK (0x0050)

UCS : Multiply Selected Loop Freq. By XT2CLK

Examples:: bootstrap/clocks/main.c.

#define SVMHE (0x4000)

SVM high side enable

Examples:: bootstrap/applpm/main.c, periph/timer/alarm/main.c, and utility/cli/main.c.

#define SVMHFP (0x8000)

SVM high side full performace mode

#define SVMHOVPE (0x1000)

SVM high side over-voltage enable

#define SVMLE (0x4000)

SVM low side enable

Examples:: bootstrap/applpm/main.c, periph/timer/alarm/main.c, and utility/cli/main.c.

#define SVMLFP (0x8000)

SVM low side full performace mode

#define SVMLOVPE (0x1000)

SVM low side over-voltage enable

#define SVSHE (0x0400)

SVS high side enable

Examples:: bootstrap/applpm/main.c, periph/timer/alarm/main.c, and utility/cli/main.c.

#define SVSHFP (0x0800)

SVS high side full performace mode

#define SVSHMD (0x0010)

SVS high side mode

#define SVSHRVL0 (0x0100)

SVS high side reset voltage level Bit: 0

#define SVSHRVL1 (0x0200)

SVS high side reset voltage level Bit: 1

#define SVSLE (0x0400)

SVS low side enable

Examples:: bootstrap/applpm/main.c, periph/timer/alarm/main.c, and utility/cli/main.c.

#define SVSLFP (0x0800)

SVS low side full performace mode

#define SVSLMD (0x0010)

SVS low side mode

#define SVSLRVL0 (0x0100)

SVS low side reset voltage level Bit: 0

#define SVSLRVL1 (0x0200)

SVS low side reset voltage level Bit: 1

#define SVSMHACE (0x0080)

SVS and SVM high side auto control enable

#define SVSMHDLYST (0x0008)

SVS and SVM high side delay status

#define SVSMHEVM (0x0040)

SVS and SVM high side event mask

#define SVSMHRRL1 (0x0002)

SVS and SVM high side Reset Release Voltage Level Bit: 1

#define SVSMHRRL2 (0x0004)

SVS and SVM high side Reset Release Voltage Level Bit: 2

#define SVSMLACE (0x0080)

SVS and SVM low side auto control enable

#define SVSMLDLYST (0x0008)

SVS and SVM low side delay status

#define SVSMLEVM (0x0040)

SVS and SVM low side event mask

#define SVSMLRRL0 (0x0001)

SVS and SVM low side Reset Release Voltage Level Bit: 0

#define SVSMLRRL1 (0x0002)

SVS and SVM low side Reset Release Voltage Level Bit: 1

#define SVSMLRRL2 (0x0004)

SVS and SVM low side Reset Release Voltage Level Bit: 2

#define SYSRSTIV_BOR (0x0002)

SYSRSTIV : BOR

#define SYSRSTIV_CCSKEY (0x0012)

SYSRSTIV : CCS Key violation

#define SYSRSTIV_CSKEY (0x0024)

SYSRSTIV : CSKEY violation

#define SYSRSTIV_CSPW (0x0024)

SYSRSTIV : CS Password violation

#define SYSRSTIV_DBDIFG (0x001C)

SYSRSTIV : FRAM Double bit Error

#define SYSRSTIV_DOBOR (0x0006)

SYSRSTIV : Do BOR

#define SYSRSTIV_DOBOR (0x0008)

SYSRSTIV : Do BOR

#define SYSRSTIV_DOPOR (0x000C)

SYSRSTIV : Do POR

#define SYSRSTIV_DOPOR (0x0014)

SYSRSTIV : Do POR

#define SYSRSTIV_FLLUL (0x001C)

SYSRSTIV : FLL unlock

#define SYSRSTIV_FRCTLPW (0x001A)

SYSRSTIV : FRAM Key violation

#define SYSRSTIV_KEYV (0x001A)

SYSRSTIV : Flash Key violation

#define SYSRSTIV_LPM5WU (0x0008)

SYSRSTIV : Port LPM5 Wake Up

#define SYSRSTIV_MPUKEY (0x0022)

SYSRSTIV : MPUKEY violation

#define SYSRSTIV_MPUPW (0x0022)

SYSRSTIV : MPU Password violation

#define SYSRSTIV_MPUSEG1IFG (0x0028)

SYSRSTIV : MPUSEG1IFG violation

#define SYSRSTIV_MPUSEG2IFG (0x002A)

SYSRSTIV : MPUSEG2IFG violation

#define SYSRSTIV_MPUSEG3IFG (0x002C)

SYSRSTIV : MPUSEG3IFG violation

#define SYSRSTIV_MPUSEGIIFG (0x0026)

SYSRSTIV : MPUSEGIIFG violation

#define SYSRSTIV_MPUSEGPIFG (0x0026)

SYSRSTIV : MPUSEGPIFG violation

#define SYSRSTIV_PERF (0x0016)

SYSRSTIV : peripheral/config area fetch

#define SYSRSTIV_PERF (0x001E)

SYSRSTIV : peripheral/config area fetch

#define SYSRSTIV_PLLUL (0x001C)

SYSRSTIV : PLL unlock

#define SYSRSTIV_PMMKEY (0x0014)

SYSRSTIV : PMMKEY violation

#define SYSRSTIV_PMMKEY (0x0020)

SYSRSTIV : PMMKEY violation

#define SYSRSTIV_PMMPW (0x0020)

SYSRSTIV : PMM Password violation

#define SYSRSTIV_PSSKEY (0x0020)

SYSRSTIV : Legacy: PMMKEY violation

#define SYSRSTIV_RSTNMI (0x0004)

SYSRSTIV : RST/NMI

#define SYSRSTIV_RSTNMI (0x0006)

SYSRSTIV : RST/NMI

#define SYSRSTIV_SECYV (0x000A)

SYSRSTIV : Security violation

#define SYSRSTIV_SVMBOR (0x0004)

SYSRSTIV : SVMBOR

#define SYSRSTIV_SVMH_OVP (0x0012)

SYSRSTIV : SVMH_OVP

#define SYSRSTIV_SVML_OVP (0x0010)

SYSRSTIV : SVML_OVP

#define SYSRSTIV_SVSH (0x000E)

SYSRSTIV : SVSH

#define SYSRSTIV_SVSHIFG (0x000E)

SYSRSTIV : SVSHIFG

#define SYSRSTIV_SVSL (0x000C)

SYSRSTIV : SVSL

#define SYSRSTIV_SVSLIFG (0x000C)

SYSRSTIV : SVSLIFG

#define SYSRSTIV_UBDIFG (0x001C)

SYSRSTIV : FRAM Uncorrectable bit Error

#define SYSRSTIV_WDTKEY (0x0010)

SYSRSTIV : WDTKEY violation

#define SYSRSTIV_WDTKEY (0x0018)

SYSRSTIV : WDTKEY violation

#define SYSRSTIV_WDTTO (0x000E)

SYSRSTIV : WDT Time out

#define SYSRSTIV_WDTTO (0x0016)

SYSRSTIV : WDT Time out

#define TAG_ADC10_1 (0x08)

(2xx) Tag for ADC10_1 Calibration Data

#define TAG_ADC12_1 (0x08)

(2xx) Tag for ADC12_1 Calibration Data

#define TAG_DCO_30 (0x01)

(2xx) Tag for DCO30 Calibration Data

#define TAG_EMPTY (0xFE)

(2xx) Tag for Empty Data Field in Calibration Data

#define TLV_ADC10CAL (0x13)

ADC10 calibration

#define TLV_ADC12CAL (0x11)

ADC12 calibration

#define TLV_ADCCAL (0x11)

ADC12 calibration

#define TLV_BLANK (0x05)

Blank descriptor

#define TLV_DIERECORD (0x08)

Die Record

#define TLV_END (0x1AFF)

End Address of the TLV structure (INCLUSIVE)

#define TLV_LDTAG (0x01)

Legacy descriptor (1xx, 2xx, 4xx families)

#define TLV_PDTAG (0x02)

Peripheral discovery descriptor

#define TLV_REFCAL (0x12)

REF calibration

#define TLV_START (0x1A08)

Start Address of the TLV structure (EXCLUDES HEADER)

#define TLV_TAGEXT (0xFE)

Tag extender

#define UC7BIT (0x10)

UART/SPI ctl0 : Async. Mode: Data Bits 0:8-bits / 1:7-bits

#define UCA10 (0x80)

I2C ctl0 : 10-bit Address Mode

#define UCBRKIE (0x10)

UART ctl1 : Break interrupt enable

#define UCBUSY (0x01)

USCI Busy Flag

#define UCCKPH (0x80)

SPI ctl0 : Sync. Mode: Clock Phase

Examples:: utility/m25p/main.c.

#define UCCKPL (0x40)

SPI ctl0 : Sync. Mode: Clock Polarity

Examples:: utility/m25p/main.c.

#define UCDORM (0x08)

UART ctl1 : Dormant (Sleep) Mode

#define UCMM (0x20)

I2C ctl0 : Multi-Master Environment

#define UCMODE_0 (0x00)

ctl0 : Sync. Mode: USCI Mode: 0 (3-pin SPI)

#define UCMODE_1 (0x02)

ctl0 : Sync. Mode: USCI Mode: 1 (4-pin SPI, m/s if STE)

#define UCMODE_2 (0x04)

ctl0 : Sync. Mode: USCI Mode: 2 (4-pin SPI, m/s if !STE)

#define UCMODE_3 (0x06)

ctl0 : Sync. Mode: USCI Mode: 3 (I2C)

#define UCMSB (0x20)

UART/SPI ctl0 : Async. Mode: MSB first 0:LSB / 1:MSB

#define UCMST (0x08)

SPI ctl0 : Sync. Mode: Master Select

Examples:: sensors/hh10d/main.c, and sensors/tmp102/main.c.

#define UCPAR (0x40)

UART ctl0 : Async. Mode: Parity 0:odd / 1:even

#define UCPEN (0x80)

UART ctl0 : Async. Mode: Parity enable

#define UCRXEIE (0x20)

UART ctl1 : RX Error interrupt enable

#define UCSLA10 (0x40)

I2C ctl0 : 10-bit Slave Address Mode

#define UCSPB (0x08)

UART ctl0 : Async. Mode: Stop Bits 0:one / 1: two

#define UCSSEL_0 (0x00)

ctl1 : USCI 0 Clock Source: 0 (NA, UCLK)

#define UCSSEL_1 (0x40)

ctl1 : USCI 0 Clock Source: 1 (ACLK)

#define UCSSEL_2 (0x80)

ctl1 : USCI 0 Clock Source: 2 (SMCLK)

Examples:: utility/m25p/main.c.

#define UCSSEL_3 (0xC0)

ctl1 : USCI 0 Clock Source: 3 (SMCLK)

#define UCSWRST (0x01)

ctl1 : USCI Software Reset

#define UCSYNC (0x01)

ctl0 : Sync-Mode 0:UART-Mode / 1:SPI-Mode

#define UCTR (0x10)

I2C ctl1 : Transmit/Receive Select/Flag

#define UCTXADDR (0x04)

UART ctl1 : Send next Data as Address

#define UCTXBRK (0x02)

UART ctl1 : Send next Data as Break

#define UCTXNACK (0x08)

I2C ctl1 : Transmit NACK

#define UCTXSTP (0x04)

I2C ctl1 : Transmit STOP

#define UCTXSTT (0x02)

I2C ctl1 : Transmit START

#define V (0x0100)

Overflow. This bit is set when the result of an arithmetic operation overflows the signed-variable range.

#define XCAP0PF (0x00)

FLL+ : XIN Cap = XOUT Cap = 0pf

#define XCAP10PF (0x10)

FLL+ : XIN Cap = XOUT Cap = 10pf

#define XCAP14PF (0x20)

FLL+ : XIN Cap = XOUT Cap = 14pf

#define XCAP18PF (0x30)

FLL+ : XIN Cap = XOUT Cap = 18pf

#define XCAP_0 (0x00)

BC2 : XIN/XOUT Cap : 0 pF

#define XCAP_1 (0x04)

BC2 : XIN/XOUT Cap : 6 pF

#define XCAP_2 (0x08)

BC2 : XIN/XOUT Cap : 10 pF

#define XCAP_3 (0x0C)

BC2 : XIN/XOUT Cap : 12.5 pF

#define Z (0x0002)

Zero. This bit is set when the result of an operation is 0 and cleared when the result is not 0.

Variable Documentation

unsigned int SVSMHCTL

SVS and SVM high side control register

Examples:: bootstrap/applpm/main.c, periph/timer/alarm/main.c, and utility/cli/main.c.

unsigned int SVSMLCTL

SVS and SVM low side control register

Examples:: bootstrap/applpm/main.c, periph/timer/alarm/main.c, and utility/cli/main.c.

Macros

Variables

Detailed Description

Macro Definition Documentation

Variable Documentation