BSP430  20141115
Board Support Package for MSP430 microcontrollers
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core.h
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1 /* Copyright 2012-2014, Peter A. Bigot
2  *
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * * Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * * Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * * Neither the name of the software nor the names of its contributors may be
16  * used to endorse or promote products derived from this software without
17  * specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
46 #ifndef BSP430_CORE_H
47 #define BSP430_CORE_H
48 
49 #include <msp430.h> /* MSP430 MCU-specific information */
50 #include <stdint.h> /* Size-annotated integral types (uint8_t) */
51 #include <stddef.h> /* NULL and size_t */
52 #include <stdbool.h> /* bool */
53 
60 #define BSP430_VERSION 20141115
61 
92 #define BSP430_PERIPH_CPPID_NONE 0
93 
94 /* !BSP430! insert=periph_cppid */
95 /* BEGIN AUTOMATICALLY GENERATED CODE---DO NOT MODIFY [periph_cppid] */
96 
98 #define BSP430_PERIPH_CPPID_PORT1 1
99 
101 #define BSP430_PERIPH_CPPID_PORT2 2
102 
104 #define BSP430_PERIPH_CPPID_PORT3 3
105 
107 #define BSP430_PERIPH_CPPID_PORT4 4
108 
110 #define BSP430_PERIPH_CPPID_PORT5 5
111 
113 #define BSP430_PERIPH_CPPID_PORT6 6
114 
116 #define BSP430_PERIPH_CPPID_PORT7 7
117 
119 #define BSP430_PERIPH_CPPID_PORT8 8
120 
122 #define BSP430_PERIPH_CPPID_PORT9 9
123 
125 #define BSP430_PERIPH_CPPID_PORT10 10
126 
128 #define BSP430_PERIPH_CPPID_PORT11 11
129 
131 #define BSP430_PERIPH_CPPID_TA0 12
132 
134 #define BSP430_PERIPH_CPPID_TA1 13
135 
137 #define BSP430_PERIPH_CPPID_TA2 14
138 
140 #define BSP430_PERIPH_CPPID_TA3 15
141 
143 #define BSP430_PERIPH_CPPID_TB0 16
144 
146 #define BSP430_PERIPH_CPPID_TB1 17
147 
149 #define BSP430_PERIPH_CPPID_TB2 18
150 
152 #define BSP430_PERIPH_CPPID_USCI_A0 19
153 
155 #define BSP430_PERIPH_CPPID_USCI_A1 20
156 
158 #define BSP430_PERIPH_CPPID_USCI_B0 21
159 
161 #define BSP430_PERIPH_CPPID_USCI_B1 22
162 
164 #define BSP430_PERIPH_CPPID_USCI5_A0 23
165 
167 #define BSP430_PERIPH_CPPID_USCI5_A1 24
168 
170 #define BSP430_PERIPH_CPPID_USCI5_A2 25
171 
173 #define BSP430_PERIPH_CPPID_USCI5_A3 26
174 
176 #define BSP430_PERIPH_CPPID_USCI5_B0 27
177 
179 #define BSP430_PERIPH_CPPID_USCI5_B1 28
180 
182 #define BSP430_PERIPH_CPPID_USCI5_B2 29
183 
185 #define BSP430_PERIPH_CPPID_USCI5_B3 30
186 
188 #define BSP430_PERIPH_CPPID_EUSCI_A0 31
189 
191 #define BSP430_PERIPH_CPPID_EUSCI_A1 32
192 
194 #define BSP430_PERIPH_CPPID_EUSCI_A2 33
195 
197 #define BSP430_PERIPH_CPPID_EUSCI_B0 34
198 /* END AUTOMATICALLY GENERATED CODE [periph_cppid] */
199 /* !BSP430! end=periph_cppid */
200 
222 #ifndef configBSP430_CORE_INCLUDE_BSP430_CONFIG_FILE
223 #define configBSP430_CORE_INCLUDE_BSP430_CONFIG_FILE 1
224 #endif /* configBSP430_CORE_INCLUDE_BSP430_CONFIG_FILE */
225 
226 #if (configBSP430_CORE_INCLUDE_BSP430_CONFIG_FILE - 0)
227 #include "bsp430_config.h"
228 #endif /* configBSP430_CORE_INCLUDE_BSP430_CONFIG_FILE */
229 
244 #ifndef BSP430_CORE_NDEBUG
245 #define BSP430_CORE_NDEBUG 0
246 #endif /* BSP430_CORE_NDEBUG */
247 
261 #if defined(__MSP430_HAS_MSP430XV2_CPU__)
262 #define BSP430_CORE_FAMILY_IS_5XX 1
263 #else /* 5xx == CPUXv2*/
264 #define BSP430_CORE_FAMILY_IS_5XX 0
265 #endif /* 5xx == CPUXv2 */
266 
296 #ifndef configBSP430_CORE_DISABLE_FLL
297 #define configBSP430_CORE_DISABLE_FLL (defined(__MSP430_HAS_UCS__) || defined(__MSP430_HAS_UCS_RF__))
298 #endif /* configBSP430_CORE_DISABLE_FLL */
299 
313 #ifndef configBSP430_CORE_LPM_EXIT_CLEAR_GIE
314 #define configBSP430_CORE_LPM_EXIT_CLEAR_GIE 0
315 #endif /* configBSP430_CORE_LPM_EXIT_CLEAR_GIE */
316 
318 #if (configBSP430_CORE_LPM_EXIT_CLEAR_GIE - 0)
319 #define BSP430_CORE_LPM_EXIT_CLEAR_GIE_ GIE
320 #else /* configBSP430_CORE_LPM_EXIT_CLEAR_GIE */
321 #define BSP430_CORE_LPM_EXIT_CLEAR_GIE_ 0
322 #endif /* configBSP430_CORE_LPM_EXIT_CLEAR_GIE */
323 
334 #ifndef BSP430_CORE_LPM_EXIT_MASK
335 #if (configBSP430_CORE_DISABLE_FLL - 0)
336 #define BSP430_CORE_LPM_EXIT_MASK (BSP430_CORE_LPM_EXIT_CLEAR_GIE_ | (LPM4_bits & ~SCG0))
337 #else /* configBSP430_CORE_DISABLE_FLL */
338 #define BSP430_CORE_LPM_EXIT_MASK (BSP430_CORE_LPM_EXIT_CLEAR_GIE_ | LPM4_bits)
339 #endif /* configBSP430_CORE_DISABLE_FLL */
340 #endif /* BSP430_CORE_LPM_EXIT_MASK */
341 
348 #define BSP430_CORE_LPM_SR_MASK (SCG1 | SCG0 | OSCOFF | CPUOFF | GIE)
349 
361 #define BSP430_CORE_LPM_LPMXp5 0x0100
362 
364 #define BSP430_CORE_TOOLCHAIN_GCC (1 < __GNUC__)
365 
367 #define BSP430_CORE_TOOLCHAIN_GCC_MSPGCC (1 < __MSPGCC__)
368 
370 #define BSP430_CORE_TOOLCHAIN_GCC_MSP430_ELF (BSP430_CORE_TOOLCHAIN_GCC && ! BSP430_CORE_TOOLCHAIN_GCC_MSPGCC)
371 
372 #if (BSP430_CORE_TOOLCHAIN_GCC_MSP430_ELF - 0)
373 #define __read_status_register() _get_SR_register()
374 #define __bis_status_register(v_) _bis_SR_register(v_)
375 #define __bic_status_register(v_) _bic_SR_register(v_)
376 #define __bic_status_register_on_exit(v_) __bic_SR_register_on_exit(v_)
377 #define __bis_status_register_on_exit(v_) __bis_SR_register_on_exit(v_)
378 #define __disable_interrupts() _disable_interrupts()
379 #define __enable_interrupts() _enable_interrupts()
380 #endif /* RHGCC */
381 
388 #define BSP430_CORE_TOOLCHAIN_LIBC_MSP430_LIBC BSP430_CORE_TOOLCHAIN_GCC_MSPGCC
389 
396 #define BSP430_CORE_TOOLCHAIN_LIBC_NEWLIB BSP430_CORE_TOOLCHAIN_GCC_MSP430_ELF
397 
410 #ifdef __TI_COMPILER_VERSION__
411 /* TI's compiler isn't GCC even if somebody added --gcc to the command
412  * line, which causes __GNUC__ to be defined (apparently as 3). */
413 #undef BSP430_CORE_TOOLCHAIN_GCC
414 #define BSP430_CORE_TOOLCHAIN_TI 1
415 #endif /* __TI_COMPILER_VERSION__ */
416 
417 #if (BSP430_CORE_TOOLCHAIN_TI - 0)
418 #define __read_stack_register() _get_SP_register()
419 #define __read_status_register() _get_SR_register()
420 #define __bis_status_register(v_) _bis_SR_register(v_)
421 #define __bic_status_register(v_) _bic_SR_register(v_)
422 #define __bic_status_register_on_exit(v_) _bic_SR_register_on_exit(v_)
423 #define __nop() _nop()
424 #endif /* BSP430_CORE_TOOLCHAIN_TI */
425 
438 #if defined(BSP430_DOXYGEN) || (BSP430_CORE_TOOLCHAIN_GCC - 0)
439 #define BSP430_CORE_INLINE __inline__
440 #elif BSP430_CORE_TOOLCHAIN_TI - 0
441 #define BSP430_CORE_INLINE __inline
442 #else /* TOOLCHAIN */
443 #define BSP430_CORE_INLINE inline
444 #endif /* TOOLCHAIN */
445 
452 #if defined(BSP430_DOXYGEN) || (BSP430_CORE_TOOLCHAIN_GCC - 0)
453 /* GCC wants both directives */
454 #define BSP430_CORE_INLINE_FORCED BSP430_CORE_INLINE __attribute__((__always_inline__))
455 #else /* TOOLCHAIN */
456 #define BSP430_CORE_INLINE_FORCED BSP430_CORE_INLINE
457 #endif /* TOOLCHAIN */
458 
467 #if defined(BSP430_DOXYGEN) || (BSP430_CORE_TOOLCHAIN_GCC - 0)
468 #define BSP430_CORE_PACKED_STRUCT(nm_) struct __attribute__((__packed__)) nm_
469 #endif /* TOOLCHAIN */
470 
478 #if (BSP430_CORE_TOOLCHAIN_TI - 0)
479 #define BSP430_CORE_DECLARE_INTERRUPT(iv_) _BSP430_CORE_TOOLCHAIN_TI_PRAGMA(vector=##iv_) __interrupt void
480 /* Helper function required to make the _Pragma argument a single
481  * string literal */
482 #define _BSP430_CORE_TOOLCHAIN_TI_PRAGMA(x_) _Pragma(#x_)
483 #else /* TOOLCHAIN */
484 #define BSP430_CORE_DECLARE_INTERRUPT(iv_) void __attribute__((__interrupt__(iv_)))
485 #endif /* TOOLCHAIN */
486 
507 #define BSP430_CORE_LPM_ENTER(lpm_bits_) __bis_status_register(BSP430_CORE_LPM_SR_MASK & (lpm_bits_))
508 
530 #define BSP430_CORE_LPM_ENTER_NI(lpm_bits_) BSP430_CORE_LPM_ENTER(GIE | (lpm_bits_))
531 
548 #define BSP430_CORE_LPM_EXIT_FROM_ISR(lpm_bits_) __bic_status_register_on_exit(BSP430_CORE_LPM_SR_MASK & (lpm_bits_))
549 
570 #ifndef configBSP430_CORE_SUPPORT_WATCHDOG
571 #define configBSP430_CORE_SUPPORT_WATCHDOG 0
572 #endif /* configBSP430_CORE_SUPPORT_WATCHDOG */
573 
591 #if (configBSP430_CORE_SUPPORT_WATCHDOG - 0)
592 #ifndef BSP430_CORE_WATCHDOG_CLEAR
593 #if 20120406 < __MSPGCC__
594 #define BSP430_CORE_WATCHDOG_CLEAR() __watchdog_clear()
595 #endif /* MSPGCC */
596 #endif /* BSP430_CORE_WATCHDOG_CLEAR */
597 #else /* configBSP430_CORE_SUPPORT_WATCHDOG */
598 #undef BSP430_CORE_WATCHDOG_CLEAR
599 #define BSP430_CORE_WATCHDOG_CLEAR() do { } while (0)
600 #endif /* configBSP430_CORE_SUPPORT_WATCHDOG */
601 
608 #ifndef BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES
609 #define BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES 10000U
610 #endif /* BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES */
611 
642 #if (configBSP430_CORE_SUPPORT_WATCHDOG - 0)
643 #define BSP430_CORE_DELAY_CYCLES(duration_mclk_) do { \
644  if ((duration_mclk_) > BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES) { \
645  unsigned int _watchdog_iterations = (duration_mclk_) / BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES; \
646  while (0 < _watchdog_iterations--) { \
647  __delay_cycles(BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES); \
648  BSP430_CORE_WATCHDOG_CLEAR(); \
649  } \
650  } \
651  __delay_cycles((duration_mclk_) % BSP430_CORE_WATCHDOG_MAX_DELAY_CYCLES); \
652  } while (0)
653 #else /* configBSP430_CORE_SUPPORT_WATCHDOG */
654 #define BSP430_CORE_DELAY_CYCLES(duration_mclk_) __delay_cycles(duration_mclk_)
655 #endif /* configBSP430_CORE_SUPPORT_WATCHDOG */
656 
661 #ifndef BSP430_CORE_INTERRUPT_STATE_T
662 #if defined(BSP430_DOXYGEN) || (BSP430_CORE_TOOLCHAIN_GCC_MSPGCC - 0)
663 #define BSP430_CORE_INTERRUPT_STATE_T __istate_t
664 #else /* TOOLCHAIN */
665 #define BSP430_CORE_INTERRUPT_STATE_T unsigned int
666 #endif /* TOOLCHAIN */
667 #endif /* BSP430_CORE_INTERRUPT_STATE_T */
668 
688 #ifndef BSP430_CORE_SAVE_INTERRUPT_STATE
689 #define BSP430_CORE_SAVE_INTERRUPT_STATE(state_) do { \
690  (state_) = __get_interrupt_state(); \
691  } while (0)
692 #endif /* BSP430_CORE_SAVE_INTERRUPT_STATE */
693 
718 #ifndef BSP430_CORE_SAVED_INTERRUPT_STATE
719 #define BSP430_CORE_SAVED_INTERRUPT_STATE(var_) \
720  BSP430_CORE_INTERRUPT_STATE_T var_ = __get_interrupt_state()
721 #endif /* BSP430_CORE_SAVED_INTERRUPT_STATE */
722 
730 #ifndef BSP430_CORE_RESTORE_INTERRUPT_STATE
731 #define BSP430_CORE_RESTORE_INTERRUPT_STATE(state_) do { \
732  __set_interrupt_state(state_); \
733  } while (0)
734 #endif /* BSP430_CORE_RESTORE_INTERRUPT_STATE */
735 
744 #ifndef BSP430_CORE_ENABLE_INTERRUPT
745 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
746 #define BSP430_CORE_ENABLE_INTERRUPT() do { \
747  __enable_interrupt(); \
748  __nop(); \
749  } while (0)
750 #else /* BSP430_CORE_FAMILY_IS_5XX */
751 #define BSP430_CORE_ENABLE_INTERRUPT() __enable_interrupt()
752 #endif /* BSP430_CORE_FAMILY_IS_5XX */
753 #endif /* BSP430_CORE_ENABLE_INTERRUPT */
754 
758 #ifndef BSP430_CORE_DISABLE_INTERRUPT
759 #if (BSP430_CORE_TOOLCHAIN_GCC_MSP430_ELF - 0)
760 #define BSP430_CORE_DISABLE_INTERRUPT() do { _disable_interrupts(); _no_operation(); } while (0)
761 #else /* BSP430_CORE_TOOLCHAIN */
762 #define BSP430_CORE_DISABLE_INTERRUPT() __disable_interrupt()
763 #endif /* BSP430_CORE_TOOLCHAIN */
764 #endif /* BSP430_CORE_DISABLE_INTERRUPT */
765 
778 #define BSP430_CORE_US_TO_TICKS(us_, hz_) (((us_) * (unsigned long)(hz_)) / 1000000UL)
779 
792 #define BSP430_CORE_TICKS_TO_US(ticks_, hz_) ((1000000UL * (ticks_)) / (hz_))
793 
806 #define BSP430_CORE_MS_TO_TICKS(ms_, hz_) (((ms_) * (unsigned long)(hz_)) / 1000UL)
807 
820 #define BSP430_CORE_TICKS_TO_MS(ticks_, hz_) ((1000UL * (ticks_)) / (hz_))
821 
826 #if (BSP430_CORE_TOOLCHAIN_GCC_MSPGCC - 0)
827 #include <byteswap.h>
828 #define BSP430_CORE_SWAP_16(w_) bswap_16(w_)
829 #elif (BSP430_CORE_TOOLCHAIN_GCC_MSP430_ELF - 0)
830 #define BSP430_CORE_SWAP_16(w_) _swap_bytes(w_)
831 #else
832 #define BSP430_CORE_SWAP_16(w_) (( ((w_) & 0xFF00) >> 8) \
833  | (((w_) & 0x00FF) << 8) )
834 #endif
835 
840 #if (BSP430_CORE_TOOLCHAIN_GCC_MSPGCC - 0)
841 #include <byteswap.h>
842 #define BSP430_CORE_SWAP_32(lw_) bswap_32(lw_)
843 #else
844 #define BSP430_CORE_SWAP_32(lw_) (( ((lw_) & 0xFF000000) >> 24) \
845  | (((lw_) & 0x00FF0000) >> 8) \
846  | (((lw_) & 0x0000FF00) << 8) \
847  | (((lw_) & 0x000000FF) << 24) )
848 #endif
849 
850 /* See <bsp430/rtos/freertos.h> */
851 #if (configBSP430_RTOS_FREERTOS - 0)
852 /* FreeRTOS defines application behavior in a shared header. Read it
853  * in here so everybody agrees on its contents. */
854 
855 #include "FreeRTOS.h"
856 
857 #define BSP430_RTOS_YIELD_FROM_ISR() portYIELD_FROM_ISR(1)
858 
859 #endif /* configBSP430_RTOS_FREERTOS */
860 
871 #ifndef BSP430_RTOS_YIELD_FROM_ISR
872 #define BSP430_RTOS_YIELD_FROM_ISR() do { } while (0)
873 #endif /* BSP430_RTOS_YIELD_FROM_ISR */
874 
875 #endif /* BSP430_CORE_H */
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