BSP430  20141115
Board Support Package for MSP430 microcontrollers
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clock.h
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1 /* Copyright 2012-2014, Peter A. Bigot
2  *
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
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30  */
31 
65 #ifndef BSP430_CLOCK_H
66 #define BSP430_CLOCK_H
67 
68 #include <bsp430/core.h>
69 
80 #define BSP430_PERIPH_CS_IS_CSA (defined(__MSP430_HAS_CS_A__) || (defined(__MSP430_HAS_CS__) && defined(DCOFSEL2)))
81 
91 #define BSP430_PERIPH_CS_IS_CS4 (defined(__MSP430_HAS_CS__) && defined(SELA))
92 
112 #ifndef BSP430_CLOCK_NOMINAL_MCLK_HZ
113 #define BSP430_CLOCK_NOMINAL_MCLK_HZ 7948800UL
114 #endif /* BSP430_CLOCK_NOMINAL_MCLK_HZ */
115 
130 #define BSP430_CLOCK_US_TO_NOMINAL_MCLK(delay_us_) BSP430_CORE_US_TO_TICKS((delay_us_), BSP430_CLOCK_NOMINAL_MCLK_HZ)
131 
148 #if defined(BSP430_DOXYGEN)
149 #define BSP430_CLOCK_LFXT1_XCAP include <bsp430/platform.h>
150 #endif /* BSP430_DOXYGEN */
151 
161 #if defined(BSP430_DOXYGEN)
162 #define BSP430_CLOCK_IS_FAULTED_NI() peripheral specific
163 #endif /* BSP430_DOXYGEN */
164 
181 #ifndef BSP430_CLOCK_FAULT_RECHECK_DELAY_US
182 #define BSP430_CLOCK_FAULT_RECHECK_DELAY_US 50
183 #endif /* BSP430_CLOCK_FAULT_RECHECK_DELAY_US */
184 
205 #if defined(BSP430_DOXYGEN)
206 #define BSP430_CLOCK_CLEAR_FAULTS_NI() peripheral specific
207 #endif /* BSP430_DOXYGEN */
208 
215 #if defined(__MSP430_HAS_MSP430XV2_CPU__)
216 #define BSP430_CLOCK_OSC_IS_FAULTED_NI() (SFRIFG1 & OFIFG)
217 #else /* 5xx */
218 #define BSP430_CLOCK_OSC_IS_FAULTED_NI() (IFG1 & OFIFG)
219 #endif /* 5xx */
220 
227 #if defined(__MSP430_HAS_MSP430XV2_CPU__)
228 #define BSP430_CLOCK_OSC_CLEAR_FAULT_NI() do { SFRIFG1 &= ~OFIFG; } while (0)
229 #else /* 5xx */
230 #define BSP430_CLOCK_OSC_CLEAR_FAULT_NI() do { IFG1 &= ~OFIFG; } while (0)
231 #endif /* 5xx */
232 
239 #if defined(BSP430_DOXYGEN)
240 #define BSP430_CLOCK_LFXT1_IS_FAULTED_NI() peripheral specific
241 #endif /* BSP430_DOXYGEN */
242 
247 #ifndef BSP430_CLOCK_XT2_IS_FAULTED_NI
248 #define BSP430_CLOCK_XT2_IS_FAULTED_NI() (1)
249 #endif /* BSP430_CLOCK_XT2_IS_FAULTED_NI */
250 
272 #ifndef BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES
273 #define BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES BSP430_CORE_MS_TO_TICKS(50, BSP430_CLOCK_PUC_MCLK_HZ)
274 #endif /* BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES */
275 
280 #ifndef BSP430_CLOCK_XT2_STABILIZATION_DELAY_CYCLES
281 #define BSP430_CLOCK_XT2_STABILIZATION_DELAY_CYCLES (20000UL)
282 #endif /* BSP430_CLOCK_XT2_STABILIZATION_DELAY_CYCLES */
283 
290 #if defined(BSP430_DOXYGEN)
291 #define BSP430_CLOCK_XT2_IS_FAULTED_NI() peripheral specific
292 #endif /* BSP430_DOXYGEN */
293 
300 #ifndef BSP430_CLOCK_NOMINAL_XT1CLK_HZ
301 #define BSP430_CLOCK_NOMINAL_XT1CLK_HZ 32768U
302 #endif /* BSP430_CLOCK_NOMINAL_XT1CLK_HZ */
303 
313 #if defined(BSP430_DOXYGEN)
314 #define BSP430_CLOCK_NOMINAL_MODCLK_HZ peripheral specific
315 #endif /* BSP430_DOXYGEN */
316 
328 #if defined(BSP430_DOXYGEN)
329 #define BSP430_CLOCK_NOMINAL_XT2CLK_HZ include <bsp430/platform.h>
330 #endif /* BSP430_DOXYGEN */
331 
342 #if defined(BSP430_DOXYGEN)
343 #define BSP430_CLOCK_NOMINAL_VLOCLK_HZ platform specific around 10-12 kHz
344 #endif /* BSP430_DOXYGEN */
345 
351 #if defined(BSP430_DOXYGEN)
352 #define BSP430_CLOCK_PUC_MCLK_HZ platform specific around 1 MHz
353 #endif /* BSP430_DOXYGEN */
354 
362 typedef enum eBSP430clockSource {
366 
371 
376 
380 
385 
389 
394 
398 
402 
406 
410 
419 
426 
437 
441 
445 
449 
453 
457 
463 
469 
471 
473 static BSP430_CORE_INLINE
474 int
477 {
478  return ((s1 == s2)
479  || ((eBSP430clockSRC_DCOCLK == s1) && (eBSP430clockSRC_DCOCLKDIV == s2))
480  || ((eBSP430clockSRC_DCOCLK == s2) && (eBSP430clockSRC_DCOCLKDIV == s1)));
481 }
482 
490 
498 
506 
561 unsigned long ulBSP430clockConfigureMCLK_ni (unsigned long mclk_Hz);
562 
575 unsigned long ulBSP430clockMCLK_Hz_ni (void);
576 
578 static BSP430_CORE_INLINE
579 unsigned long
581 {
583  unsigned long rv;
584 
588  return rv;
589 }
590 
612  unsigned int dividing_shift);
613 
617 unsigned long ulBSP430clockSMCLK_Hz_ni (void);
618 
620 static BSP430_CORE_INLINE
621 unsigned long
623 {
625  unsigned long rv;
626 
630  return rv;
631 }
632 
665 int iBSP430clockConfigureLFXT1_ni (int enablep,
666  int loop_limit);
667 
675 int iBSP430clockConfigureXT2_ni (int enablep,
676  int loop_limit);
677 
699  unsigned int dividing_shift);
700 
716 unsigned long ulBSP430clockACLK_Hz_ni (void);
717 
719 static BSP430_CORE_INLINE
720 unsigned long
722 {
724  unsigned long rv;
725 
729  return rv;
730 }
731 
738 static BSP430_CORE_INLINE
739 unsigned int
741 {
742  return ulBSP430clockACLK_Hz_ni();
743 }
744 
747 static BSP430_CORE_INLINE
748 unsigned int
750 {
752  unsigned int rv;
753 
757  return rv;
758 }
759 
760 /* Include peripheral-specific header where recognized */
761 #if defined(__MSP430_HAS_BC2__)
762 #include <bsp430/periph/bc2.h>
763 #endif /* __MSP430_HAS_BC2__ */
764 #if defined(__MSP430_HAS_FLLPLUS__) || defined(__MSP430_HAS_FLLPLUS_SMALL__)
765 #include <bsp430/periph/fllplus.h>
766 #endif /* __MSP430_HAS_FLLPLUS__ */
767 #if defined(__MSP430_HAS_UCS__) || defined(__MSP430_HAS_UCS_RF__)
768 #include <bsp430/periph/ucs.h>
769 #endif /* __MSP430_HAS_UCS__ */
770 #if defined(__MSP430_HAS_CS__) || defined(__MSP430_HAS_CS_A__)
771 #if (BSP430_PERIPH_CS_IS_CS4 - 0)
772 #include <bsp430/periph/cs4.h>
773 #else /* BSP430_PERIPH_CS_IS_CS4 */
774 #include <bsp430/periph/cs.h>
775 #endif /* BSP430_PERIPH_CS_IS_CS4 */
776 #endif /* __MSP430_HAS_CS__ */
777 
778 #endif /* BSP430_CLOCK_H */
eBSP430clockSource xBSP430clockMCLKSource()
eBSP430clockSource xBSP430clockACLKSource()
Hardware presentation/abstraction for Clock System (CS) on FR4xx/2xx chips.
#define BSP430_CORE_RESTORE_INTERRUPT_STATE(state_)
Definition: core.h:731
Definition: clock.h:393
Definition: clock.h:436
Definition: clock.h:440
Hardware presentation/abstraction for Unified Clock System (UCS).
Definition: clock.h:379
static BSP430_CORE_INLINE unsigned long ulBSP430clockMCLK_Hz(void)
Definition: clock.h:580
Definition: clock.h:418
Common header included by all BSP430 leaf headers.
static BSP430_CORE_INLINE unsigned int uiBSP430clockACLK_Hz_ni(void)
Definition: clock.h:740
Definition: clock.h:444
Definition: clock.h:409
static BSP430_CORE_INLINE unsigned int uiBSP430clockACLK_Hz(void)
Definition: clock.h:749
unsigned long ulBSP430clockACLK_Hz_ni(void)
Definition: clock.h:448
eBSP430clockSource
Definition: clock.h:362
static BSP430_CORE_INLINE unsigned long ulBSP430clockSMCLK_Hz(void)
Definition: clock.h:622
Definition: clock.h:375
Hardware presentation/abstraction for FLL Plus (FLLPLUS).
static BSP430_CORE_INLINE unsigned long ulBSP430clockACLK_Hz(void)
Definition: clock.h:721
Hardware presentation/abstraction for Clock System (CS).
Definition: clock.h:452
#define BSP430_CORE_INLINE
Definition: core.h:439
static BSP430_CORE_INLINE int iBSP430clockSourceSynchronous(eBSP430clockSource s1, eBSP430clockSource s2)
Definition: clock.h:475
Definition: clock.h:397
#define BSP430_CORE_SAVED_INTERRUPT_STATE(var_)
Definition: core.h:719
Definition: clock.h:388
int iBSP430clockConfigureACLK_ni(eBSP430clockSource sel, unsigned int dividing_shift)
int iBSP430clockConfigureXT2_ni(int enablep, int loop_limit)
Definition: clock.h:456
unsigned long ulBSP430clockMCLK_Hz_ni(void)
int iBSP430clockConfigureLFXT1_ni(int enablep, int loop_limit)
Definition: clock.h:425
#define BSP430_CORE_DISABLE_INTERRUPT()
Definition: core.h:762
Definition: clock.h:370
Definition: clock.h:462
int iBSP430clockConfigureSMCLK_ni(eBSP430clockSource sel, unsigned int dividing_shift)
Definition: clock.h:384
Definition: clock.h:401
Definition: clock.h:405
Definition: clock.h:365
Definition: clock.h:468
unsigned long ulBSP430clockConfigureMCLK_ni(unsigned long mclk_Hz)
unsigned long ulBSP430clockSMCLK_Hz_ni(void)
Hardware presentation/abstraction for Basic Clock Module+ (BC2).
eBSP430clockSource xBSP430clockSMCLKSource()