clock.h

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/* Copyright 2012-2014, Peter A. Bigot
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * * Neither the name of the software nor the names of its contributors may be
 *   used to endorse or promote products derived from this software without
 *   specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef BSP430_CLOCK_H
#define BSP430_CLOCK_H

#include <bsp430/core.h>

#define BSP430_PERIPH_CS_IS_CSA (defined(__MSP430_HAS_CS_A__) || (defined(__MSP430_HAS_CS__) && defined(DCOFSEL2)))

#define BSP430_PERIPH_CS_IS_CS4 (defined(__MSP430_HAS_CS__) && defined(SELA))

#ifndef BSP430_CLOCK_NOMINAL_MCLK_HZ
#define BSP430_CLOCK_NOMINAL_MCLK_HZ 7948800UL
#endif /* BSP430_CLOCK_NOMINAL_MCLK_HZ */

#define BSP430_CLOCK_US_TO_NOMINAL_MCLK(delay_us_) BSP430_CORE_US_TO_TICKS((delay_us_), BSP430_CLOCK_NOMINAL_MCLK_HZ)

#if defined(BSP430_DOXYGEN)
#define BSP430_CLOCK_LFXT1_XCAP include <bsp430/platform.h>
#endif /* BSP430_DOXYGEN */

#if defined(BSP430_DOXYGEN)
#define BSP430_CLOCK_IS_FAULTED_NI() peripheral specific
#endif /* BSP430_DOXYGEN */

#ifndef BSP430_CLOCK_FAULT_RECHECK_DELAY_US
#define BSP430_CLOCK_FAULT_RECHECK_DELAY_US 50
#endif /* BSP430_CLOCK_FAULT_RECHECK_DELAY_US */

#if defined(BSP430_DOXYGEN)
#define BSP430_CLOCK_CLEAR_FAULTS_NI() peripheral specific
#endif /* BSP430_DOXYGEN */

#if defined(__MSP430_HAS_MSP430XV2_CPU__)
#define BSP430_CLOCK_OSC_IS_FAULTED_NI() (SFRIFG1 & OFIFG)
#else /* 5xx */
#define BSP430_CLOCK_OSC_IS_FAULTED_NI() (IFG1 & OFIFG)
#endif /* 5xx */

#if defined(__MSP430_HAS_MSP430XV2_CPU__)
#define BSP430_CLOCK_OSC_CLEAR_FAULT_NI() do { SFRIFG1 &= ~OFIFG; } while (0)
#else /* 5xx */
#define BSP430_CLOCK_OSC_CLEAR_FAULT_NI() do { IFG1 &= ~OFIFG; } while (0)
#endif /* 5xx */

#if defined(BSP430_DOXYGEN)
#define BSP430_CLOCK_LFXT1_IS_FAULTED_NI() peripheral specific
#endif /* BSP430_DOXYGEN */

#ifndef BSP430_CLOCK_XT2_IS_FAULTED_NI
#define BSP430_CLOCK_XT2_IS_FAULTED_NI() (1)
#endif /* BSP430_CLOCK_XT2_IS_FAULTED_NI */

#ifndef BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES
#define BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES BSP430_CORE_MS_TO_TICKS(50, BSP430_CLOCK_PUC_MCLK_HZ)
#endif /* BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES */

#ifndef BSP430_CLOCK_XT2_STABILIZATION_DELAY_CYCLES
#define BSP430_CLOCK_XT2_STABILIZATION_DELAY_CYCLES (20000UL)
#endif /* BSP430_CLOCK_XT2_STABILIZATION_DELAY_CYCLES */

#if defined(BSP430_DOXYGEN)
#define BSP430_CLOCK_XT2_IS_FAULTED_NI() peripheral specific
#endif /* BSP430_DOXYGEN */

#ifndef BSP430_CLOCK_NOMINAL_XT1CLK_HZ
#define BSP430_CLOCK_NOMINAL_XT1CLK_HZ 32768U
#endif /* BSP430_CLOCK_NOMINAL_XT1CLK_HZ */

#if defined(BSP430_DOXYGEN)
#define BSP430_CLOCK_NOMINAL_MODCLK_HZ peripheral specific
#endif /* BSP430_DOXYGEN */

#if defined(BSP430_DOXYGEN)
#define BSP430_CLOCK_NOMINAL_XT2CLK_HZ include <bsp430/platform.h>
#endif /* BSP430_DOXYGEN */

#if defined(BSP430_DOXYGEN)
#define BSP430_CLOCK_NOMINAL_VLOCLK_HZ platform specific around 10-12 kHz
#endif /* BSP430_DOXYGEN */

#if defined(BSP430_DOXYGEN)
#define BSP430_CLOCK_PUC_MCLK_HZ platform specific around 1 MHz
#endif /* BSP430_DOXYGEN */

typedef enum eBSP430clockSource {
  eBSP430clockSRC_NONE,

  eBSP430clockSRC_XT1CLK,

  eBSP430clockSRC_VLOCLK,

  eBSP430clockSRC_REFOCLK,

  eBSP430clockSRC_DCOCLK,

  eBSP430clockSRC_DCOCLKDIV,

  eBSP430clockSRC_SMCLK_PU_DEFAULT,

  eBSP430clockSRC_XT2CLK,

  eBSP430clockSRC_HFXTCLK = eBSP430clockSRC_XT2CLK,

  eBSP430clockSRC_MODCLK,

  eBSP430clockSRC_LFMODCLK,

  eBSP430clockSRC_XT1CLK_OR_VLOCLK,

  eBSP430clockSRC_XT1CLK_OR_REFOCLK,

  eBSP430clockSRC_XT1CLK_FALLBACK,

  eBSP430clockSRC_UNKNOWN_1,

  eBSP430clockSRC_UNKNOWN_4,

  eBSP430clockSRC_UNKNOWN_5,

  eBSP430clockSRC_UNKNOWN_6,

  eBSP430clockSRC_UNKNOWN_7,

  eBSP430clockSRC_TCLK,

  eBSP430clockSRC_ITCLK,

} eBSP430clockSource;

static BSP430_CORE_INLINE
int
iBSP430clockSourceSynchronous (eBSP430clockSource s1,
                               eBSP430clockSource s2)
{
  return ((s1 == s2)
          || ((eBSP430clockSRC_DCOCLK == s1) && (eBSP430clockSRC_DCOCLKDIV == s2))
          || ((eBSP430clockSRC_DCOCLK == s2) && (eBSP430clockSRC_DCOCLKDIV == s1)));
}

eBSP430clockSource xBSP430clockACLKSource ();

eBSP430clockSource xBSP430clockSMCLKSource ();

eBSP430clockSource xBSP430clockMCLKSource ();

unsigned long ulBSP430clockConfigureMCLK_ni (unsigned long mclk_Hz);

unsigned long ulBSP430clockMCLK_Hz_ni (void);

static BSP430_CORE_INLINE
unsigned long
ulBSP430clockMCLK_Hz (void)
{
  BSP430_CORE_SAVED_INTERRUPT_STATE(istate);
  unsigned long rv;

  BSP430_CORE_DISABLE_INTERRUPT();
  rv = ulBSP430clockMCLK_Hz_ni();
  BSP430_CORE_RESTORE_INTERRUPT_STATE(istate);
  return rv;
}

int iBSP430clockConfigureSMCLK_ni (eBSP430clockSource sel,
                                   unsigned int dividing_shift);

unsigned long ulBSP430clockSMCLK_Hz_ni (void);

static BSP430_CORE_INLINE
unsigned long
ulBSP430clockSMCLK_Hz (void)
{
  BSP430_CORE_SAVED_INTERRUPT_STATE(istate);
  unsigned long rv;

  BSP430_CORE_DISABLE_INTERRUPT();
  rv = ulBSP430clockSMCLK_Hz_ni();
  BSP430_CORE_RESTORE_INTERRUPT_STATE(istate);
  return rv;
}

int iBSP430clockConfigureLFXT1_ni (int enablep,
                                   int loop_limit);

int iBSP430clockConfigureXT2_ni (int enablep,
                                 int loop_limit);

int iBSP430clockConfigureACLK_ni (eBSP430clockSource sel,
                                  unsigned int dividing_shift);

unsigned long ulBSP430clockACLK_Hz_ni (void);

static BSP430_CORE_INLINE
unsigned long
ulBSP430clockACLK_Hz (void)
{
  BSP430_CORE_SAVED_INTERRUPT_STATE(istate);
  unsigned long rv;

  BSP430_CORE_DISABLE_INTERRUPT();
  rv = ulBSP430clockACLK_Hz_ni();
  BSP430_CORE_RESTORE_INTERRUPT_STATE(istate);
  return rv;
}

static BSP430_CORE_INLINE
unsigned int
uiBSP430clockACLK_Hz_ni (void)
{
  return ulBSP430clockACLK_Hz_ni();
}

static BSP430_CORE_INLINE
unsigned int
uiBSP430clockACLK_Hz (void)
{
  BSP430_CORE_SAVED_INTERRUPT_STATE(istate);
  unsigned int rv;

  BSP430_CORE_DISABLE_INTERRUPT();
  rv = uiBSP430clockACLK_Hz_ni();
  BSP430_CORE_RESTORE_INTERRUPT_STATE(istate);
  return rv;
}

/* Include peripheral-specific header where recognized */
#if defined(__MSP430_HAS_BC2__)
#include <bsp430/periph/bc2.h>
#endif /* __MSP430_HAS_BC2__ */
#if defined(__MSP430_HAS_FLLPLUS__) || defined(__MSP430_HAS_FLLPLUS_SMALL__)
#include <bsp430/periph/fllplus.h>
#endif /* __MSP430_HAS_FLLPLUS__ */
#if defined(__MSP430_HAS_UCS__) || defined(__MSP430_HAS_UCS_RF__)
#include <bsp430/periph/ucs.h>
#endif /* __MSP430_HAS_UCS__ */
#if defined(__MSP430_HAS_CS__) || defined(__MSP430_HAS_CS_A__)
#if (BSP430_PERIPH_CS_IS_CS4 - 0)
#include <bsp430/periph/cs4.h>
#else /* BSP430_PERIPH_CS_IS_CS4 */
#include <bsp430/periph/cs.h>
#endif /* BSP430_PERIPH_CS_IS_CS4 */
#endif /* __MSP430_HAS_CS__ */

#endif /* BSP430_CLOCK_H */