BSP430
20141115
Board Support Package for MSP430 microcontrollers
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Hardware presentation/abstraction for Basic Clock Module+ (BC2). More...
Go to the source code of this file.
Macros | |
#define | BSP430_MODULE_BC2 defined(__MSP430_HAS_BC2__) |
#define | configBSP430_BC2_TRIM_TO_MCLK 0 |
#define | BSP430_BC2_TRIM_TO_MCLK include <bsp430/platform.h> |
#define | BSP430_BC2_LFXT1_IS_FAULTED_NI() (BCSCTL3 & BSP430_BC2_LFXT1OF_) |
#define | BSP430_BC2_XT2_IS_FAULTED_NI() (BC2CTL3 & BSP430_BC2_XT2OF_) |
#define | BSP430_CLOCK_LFXT1_IS_FAULTED_NI() ((BCSCTL3 & (LFXT1S0 | LFXT1S1)) || BSP430_BC2_LFXT1_IS_FAULTED_NI()) |
#define | BSP430_CLOCK_XT2_IS_FAULTED_NI() ((BCSCTL1 & XT2OFF) || BSP430_BC2_XT2_IS_FAULTED_NI()) |
#define | BSP430_CLOCK_CLEAR_FAULTS_NI() |
#define | BSP430_CLOCK_LFXT1_XCAP XCAP_1 |
#define | BSP430_CLOCK_NOMINAL_VLOCLK_HZ 12000U |
#define | BSP430_CLOCK_PUC_MCLK_HZ 1100000UL |
Functions | |
int | iBSP430bc2TrimToMCLK_ni (unsigned long mclk_Hz) |
Hardware presentation/abstraction for Basic Clock Module+ (BC2).
The BC2 ("Basic Clock Module+") peripheral is present in 2xx-family devices.
As there can be only one instance of BC2 on any MCU, there is no structure supporting a BC2 HPL. Manipulate the peripheral through its registers directly.
As there can be only one instance of BC2 on any MCU, there is no structure supporting a BC2 HAL.
The standard set of capabilities in the bsp430/clocks.h header are supported, with the following details:
factory-calibrated constants supporting that frequency. The selected frequency may be above or below the requested frequency, but will be the closest supported by available calibrated clocks.
#define BSP430_BC2_LFXT1_IS_FAULTED_NI | ( | ) | (BCSCTL3 & BSP430_BC2_LFXT1OF_) |
BC2-specific check for LFXT1 crystal fault condition.
This checks exactly for the fault condition.
#define BSP430_BC2_TRIM_TO_MCLK include <bsp430/platform.h> |
Defined to a true value if configBSP430_BC2_TRIM_TO_MCLK was requested and BSP430_TIMER_CCACLK is available on the platform.
In the absence of this flag, iBSP430bc2TrimToMCLK_ni() will not be available and must not be referenced.
#define BSP430_BC2_XT2_IS_FAULTED_NI | ( | ) | (BC2CTL3 & BSP430_BC2_XT2OF_) |
BC2-specific check for XT2 crystal fault condition.
If the platform does not support an XT2 crystal no fault is diagnosed.
#define BSP430_CLOCK_CLEAR_FAULTS_NI | ( | ) |
Clear all clock faults.
The BC2 oscillator fault flags are read-only, so this only clears the system oscillator flag.
#define BSP430_CLOCK_LFXT1_IS_FAULTED_NI | ( | ) | ((BCSCTL3 & (LFXT1S0 | LFXT1S1)) || BSP430_BC2_LFXT1_IS_FAULTED_NI()) |
Check whether the BC2-controlled LFXT1 crystal has a fault condition.
#define BSP430_CLOCK_LFXT1_XCAP XCAP_1 |
Peripheral default setting for platform-specific constant
#define BSP430_CLOCK_NOMINAL_VLOCLK_HZ 12000U |
Unconditional define for peripheral-specific constant
#define BSP430_CLOCK_PUC_MCLK_HZ 1100000UL |
Unconditional define for peripheral-specific constant
#define BSP430_CLOCK_XT2_IS_FAULTED_NI | ( | ) | ((BCSCTL1 & XT2OFF) || BSP430_BC2_XT2_IS_FAULTED_NI()) |
Check whether the BC2-controlled XT2 crystal has a fault condition.
#define BSP430_MODULE_BC2 defined(__MSP430_HAS_BC2__) |
Defined on inclusion of <bsp430/periph/bc2.h>. The value evaluates to true if the target MCU supports the Basic Clock Module+, and false if it does not.
#define configBSP430_BC2_TRIM_TO_MCLK 0 |
Define to a true value to request that ulBSP430bc2TrimToMCLK_ni() be made available.
Because implementation of this function depends on BSP430_TIMER_CCACLK, setting this option causes <bsp430/platform/bsp430_config.h> to default configBSP430_TIMER_CCACLK to true.
This value represents an application or system request for the feature; availability of the feature must be tested using BSP430_BC2_TRIM_TO_MCLK before attempting to invoke the function.
int iBSP430bc2TrimToMCLK_ni | ( | unsigned long | mclk_Hz | ) |
Adjust the DCO as necessary to reach the requested MCLK speed
nThe BC2 peripheral supports only a small number of calibrated DCO clock frequencies, and it is not uncommon for them to be off by a significant amount for the cheaper ValueLine MCUs. If an ACLK source at a trusted rate is available, the MCU can implement a loop to converge on a DCO configuration that supports a specific requested clock speed.