gpio.h File Reference

Support for peripheral pin multiplexing configuration. More...

#include <bspacm/core.h>

Go to the source code of this file.

Data Structures
struct	sBSPACMdeviceTM4Cpinmux

Typedefs
typedef struct sBSPACMdeviceTM4Cpinmux	sBSPACMdeviceTM4Cpinmux

Functions
void	vBSPACMdeviceTM4CpinmuxConfigure (const sBSPACMdeviceTM4Cpinmux *cfgp, int enablep)
static BSPACM_CORE_INLINE int	iBSPACMdeviceTM4CgpioPortTagFromShift (unsigned int shift)
static BSPACM_CORE_INLINE int	iBSPACMdeviceTM4CgpioPortShift (void *gpio)

Detailed Description

Support for peripheral pin multiplexing configuration.

TM4C peripherals are mapped to specific GPIO pins; the specific peripheral function supported by a GPIO pin is determined by the value written to the corresponding GPIOPCTL port control register.

The mapping between pin and peripheral function is constrained by the specific device. In some cases the same function can be mapped to multiple pins; in that situation, the desired mapping may be specific to the board or even to the application.

This file declares arrays that provide pin mapping definitions for all peripherals that are used by the application. These mappings are used by the generic TM4C peripheral configuration routines. The application, board, or device should provide definitions for the structure corresponding to each required peripheral in a source file named periph_config.c with an absolute path set in the make variable PERIPH_CONFIG_SRC. By default the board-specific periph_config.c is used.

Configuring GPIO Pins on TM4C Microcontrollers

This material adapted from my Stellarisiti forum post on TM4C123 10.3 Initialization and Configuration steps, repeated here as an easier-to-find reference:

• (1) Enable the module port, if not done already. Wait 3 cycles after enabling.

  BSPACM_CORE_BITBAND_PERIPH(SYSCTL->RCGCGPIO, iBSPACMdeviceTM4CgpioPortShift(GPIO_PORT)) = 1;
  __NOP(); __NOP(); __NOP(); // delay 3 cycles

• (1.5) Unlock any bits in CR if necessary (n1)
• (2) Configure DIR if necessary (n2)

  BSPACM_CORE_BITBAND_PERIPH(GPIO_PORT->DIR, GPIO_PIN) = 1;

• (3) Configure AFSEL
• (4) Set one of DR2R, DR4R, DR8R (n3)
• (5a) Set PUR or PDR, or clear both (n4)
• (5b) Configure ODR (n4)
• (5c) Configure SLR if using 8mA drive strength
• (6) Configure DEN and (if necessary) AMSEL
• (7) Configure interrupts (see details in 10.3 step 7)
• (8) Optionally restore the lock bit. Note that the description in 10.3 step 8 is misleading: this is not a bit in GPIOLOCK, it is a bit in GPIOCR which requires a set of the GPIOLOCK key before being modified.

Notes:

• (n1) Bits that are JTAG/SWD pins or NMI pins; see 10.2.4 and the GPIOLOCK and GPIOCR register descriptions. In library code you can simply check the CR bit: if it's clear, modifications require the unlock process.

• (n2) For some peripheral functions (e.g. UART) this bit is don't-care. See Table 10-3 "GPIO Pad Configuration Examples".

• (n3) It's unclear to me whether it is meaningful to set a zero mA drive strength by clearing a bit in all three registers, although this can be done.

• (n4) Table 10-3 suggests that ODR and PUR/PDR should be configured in certain cases regardless of direction, and should not be considered a "pick one of the three options" situation as implied by the description in section 10.3 step 5.

TM4C129 devices have extended drive that supports 6mA, 10mA, and 12mA drive strengths, but the DR2R DR4R and DR8R registers are documented to behave the same as the TM4C123 ones. The techniques required to select these strengths are not addressed here; see a TM4C129x datasheet for details.

Homepage

http://github.com/pabigot/bspacm

Copyright

Copyright 2014, Peter A. Bigot. Licensed under BSD-3-Clause

Typedef Documentation

typedef struct sBSPACMdeviceTM4Cpinmux sBSPACMdeviceTM4Cpinmux

Core structure associating a GPIO port, pin, and port control function.

Note

An all-zero pinmux denotes an unconfigured GPIO due to #pctl being zero.

Function Documentation

static BSPACM_CORE_INLINE int iBSPACMdeviceTM4CgpioPortShift ( void *  gpio )

static

Determine the bit position for a specific port within a register.

This maps, for example, GPIOK to 9 because bit 9 of a register like @ RCGCGPIO corresponds to GPIOK.

See also

iBSPACMdeviceTM4CgpioPortTagFromShift

Parameters

gpio	a reference to the port instance; generically a pointer with the bit value of the port base address. You can pass GPIOA or as appropriate.

Returns

a non-negative shift value, or -1 if gpio does not appear to be a valid port address.

static BSPACM_CORE_INLINE int iBSPACMdeviceTM4CgpioPortTagFromShift ( unsigned int  shift )

static

Convert a port instance index (shift) to the letter tag for the port.

This adjustment accounts for GPIOI and GPIOO being skipped in the letter identification, with the corresponding shifts being applied to the next supported port.

Parameters

shift

the bit index for the port

Returns

an upper-case letter corresponding to the port with 'I' and 'O' being skipped.

void vBSPACMdeviceTM4CpinmuxConfigure	(	const sBSPACMdeviceTM4Cpinmux *	cfgp,
		int	enablep
	)

Set the AFSEL bit and other bits required to configure a pin for a peripheral function according to *cfgp, or when disabled to be treated as a GPIO input.

Where cfgp->pctl is not zero (pin provides a peripheral function): Disabling the device disables the pin entirely (clears the DEN bit).

Where cfg->pctl is zero (pin provides GPIO): Enabling configures the pin for output; disabling configures the pin for input. This API is inadequate for full control as lacks the ability to set GPIO output initial state, or GPIO input pullup/pulldown state.

Note

Pins that happen to be commit-control locked will be unlocked to perform this reconfiguration then re-locked.

Warning

Pins with special considerations may, when disabled, lose their special function: this routine does not return them to their power-up configuration.

Parameters

cfgp	pointer to the configuration structure. If cfgp->port is null, no configuration will be performed.
enablep	nonzero if the pin is to be configured based on cfgp->pctl (it will be a GPIO output if cfgp->pctl is zero). If enablep is zero the pin will be disabled (or configured as a GPIO input if cfgp->pctl is zero).