Common header included by all BSPACM leaf headers. More...

#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include <bspacm/device.h>
#include <bspacm/config.h>

Macros
#define	BSPACM_CORE_INLINE __inline__

#define	BSPACM_CORE_INLINE_FORCED BSPACM_CORE_INLINE __attribute__((__always_inline__))

#define	BSPACM_CORE_PACKED_STRUCT(nm_) struct __attribute__((__packed__)) nm_

#define	BSPACM_CORE_ALIGNED_OBJECT(sz_) __attribute__((__aligned__(sz_)))

#define	BSPACM_VERSION 20150113

#define	BSPACM_CORE_DISABLE_INTERRUPT() __disable_irq()

#define	BSPACM_CORE_ENABLE_INTERRUPT() __enable_irq()

#define	BSPACM_CORE_SAVED_INTERRUPT_STATE(var_) unsigned int const var_ = __get_PRIMASK()

#define	BSPACM_CORE_RESTORE_INTERRUPT_STATE(var_)

#define	BSPACM_CORE_REENABLE_INTERRUPT(var_)

#define	BSPACM_CORE_SLEEP()

#define	BSPACM_CORE_DEEP_SLEEP()

#define	BSPACM_CORE_SUPPORTS_CYCCNT 0

#define	BSPACM_CORE_ENABLE_CYCCNT() do { } while (0)

#define	BSPACM_CORE_DISABLE_CYCCNT() do { } while (0)

#define	BSPACM_CORE_CYCCNT() 0

#define	BSPACM_CORE_DELAY_CYCLES(cycles_)

#define	BSPACM_CORE_BITBAND_SRAM32(object_, bit_) ((volatile uint32_t )BSPACM_CORE_BITBAND_SRAM_(object_, bit_))

#define	BSPACM_CORE_BITBAND_SRAM16(object_, bit_) ((volatile uint16_t )BSPACM_CORE_BITBAND_SRAM_(object_, bit_))

#define	BSPACM_CORE_BITBAND_SRAM8(object_, bit_) ((volatile uint8_t )BSPACM_CORE_BITBAND_SRAM_(object_, bit_))

#define	BSPACM_CORE_BITBAND_PERIPH(object_, bit_) ((volatile uint32_t )(BSPACM_CORE_PERIPH_BITBAND_BASE + 4 * ((bit_) + 8 * ((uintptr_t)&(object_) - BSPACM_CORE_PERIPH_BASE))))

Functions
static BSPACM_CORE_INLINE unsigned int	uiBSPACMcoreBitFromMask (uint32_t mask)

static BSPACM_CORE_INLINE void	vBSPACMcoreSetPinNybble (volatile uint32_t *basep, unsigned int pin, unsigned int value)

Detailed Description

Common header included by all BSPACM leaf headers.

Homepage: http://github.com/pabigot/bspacm

Copyright: Copyright 2014, Peter A. Bigot. Licensed under BSD-3-Clause

Macro Definition Documentation

#define BSPACM_CORE_ALIGNED_OBJECT ( sz_ ) __attribute__((__aligned__(sz_)))

Declare an aligned object a toolchain-specific manner.

Parameters

sz_	alignment requirements in bytes. E.g. to ensure the lower 10 bits of the address are zero, use 1024.

This expands to a toolchain-specific directive that controls the alignment of the following object definition. It is used for structures that are placed in system memory but accessed through peripherals, such as the micro-DMA peripheral.

#define BSPACM_CORE_BITBAND_PERIPH	(	object_,
		bit_
	)	((volatile uint32_t )(BSPACM_CORE_PERIPH_BITBAND_BASE + 4 * ((bit_) + 8 * ((uintptr_t)&(object_) - BSPACM_CORE_PERIPH_BASE))))

Bit-band reference into a peripheral register.

This is particularly useful to reduce code size when the bit and the peripheral register address are compile-time constants, as a read-modify-write instruction sequence will be replaced by a single store.

Note: Only supported on processors that use bit-banding (e.g. Cortex-M3, Cortex-M4). This macro will not be defined if the feature is not supported.

Warning: Not all peripherals will support bit-banding.

Parameters

object_	a reference to the peripheral register (not its address).
bit_	the bit of interest within `object_` (0 to 31)

Returns: an lvalue reference to a volatile uint32_t object in which bit 0 aliases bit bit_ of object_ and no other bits are used.

#define BSPACM_CORE_BITBAND_SRAM16	(	object_,
		bit_
	)	((volatile uint16_t )BSPACM_CORE_BITBAND_SRAM_(object_, bit_))

Bit-band reference into an 16-bit object in SRAM.

See also: BSPACM_CORE_BITBAND_SRAM32

#define BSPACM_CORE_BITBAND_SRAM32	(	object_,
		bit_
	)	((volatile uint32_t )BSPACM_CORE_BITBAND_SRAM_(object_, bit_))

Bit-band reference into an 32-bit object in SRAM.

This is particularly useful when manipulating a single flag in a volatile object aggregating event flags while interrupts are enabled.

Note: Only supported on processors that use bit-banding (e.g. Cortex-M3, Cortex-M4). This macro will not be defined if the feature is not supported.

Parameters

object_	a reference to (not the address of) a 32-bit object located in SRAM
bit_	the bit of interest within `object_` (0 to 31, depending on size of object)

Returns: an lvalue reference to a volatile bool object in which bit 0 aliases bit bit_ of object_ and no other bits are used.

#define BSPACM_CORE_BITBAND_SRAM8	(	object_,
		bit_
	)	((volatile uint8_t )BSPACM_CORE_BITBAND_SRAM_(object_, bit_))

Bit-band reference into an 8-bit object in SRAM.

See also: BSPACM_CORE_BITBAND_SRAM32

#define BSPACM_CORE_CYCCNT ( ) 0

Returns the current value of the cycle counter.

This returns a constant 0 if the cycle counter is not supported. (It returns an arbitrary constant if the cycle counter is supported but you didn't invoke BSPACM_CORE_ENABLE_CYCCNT()).

Dependency:: BSPACM_CORE_SUPPORTS_CYCCNT

See also: BSPACM_CORE_ENABLE_CYCCNT()

#define BSPACM_CORE_DEEP_SLEEP ( )

Value:

do {                           \
    uint32_t in_sleepdeep = (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk); \
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;                          \
    __WFI();                                                    \
    SCB->SCR &= ~in_sleepdeep;                                  \
  } while(0)

Enter the Cortex-M deep sleep mode.

The specific effect of this is vendor-specific, but in concept it turns off the processor clock and any number of other clocks. The implementation may map to a vendor-specific function or macro, but is expected to be roughly equivalent to invoking the ARM instruction WFI (or WFE) with the SLEEPDEEP bit of the System Control Register set.

Warning: The implementation of this operation is device-specific. In particular, it may include restoration of some or all peripheral clocks.

Note: The user should be aware of the effect of this operation on the hardware an application targets. Interrupts that cause wakeup will, if not masked through PRIMASK, be executed prior to control returning to the point following the __WFI() operation, meaning that any clocks disabled by the operation will not be restored until interrupt processing completes and control returns to the remainder of this macro.

Warning: Although some vendor implementations may leave the SLEEPDEEP bit set, it SHOULD be restored to its original state in the BSPACM implementation of this macro so that subsequent use of __WFI() and __WFE() executes regular or deep sleep in accordance with the original setting.

See also: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CHDJJHJI.html

#define BSPACM_CORE_DELAY_CYCLES ( cycles_ )

Value:

do {  \
    uint32_t const cycles_per_iter = 3;         \
    uint32_t remaining = (cycles_);             \
    while (remaining > cycles_per_iter) {       \
      remaining -= cycles_per_iter;             \
    }                                           \
  } while (0)

Delay for a specified number of cycles.

This does not attempt to account for the overhead of the loop.

Warning: On architectures that do not support a cycle counter, this is a rough estimate based on cycles-per-iteration of a loop.

#define BSPACM_CORE_DISABLE_CYCCNT ( ) do { } while (0)

Functional macro to disable the cycle-counting capability of the core Data Watchpoint and Trace unit.

#define BSPACM_CORE_DISABLE_INTERRUPT ( ) __disable_irq()

Gratuitous alternative spelling of standard CMSIS core intrinsic.

#define BSPACM_CORE_ENABLE_CYCCNT ( ) do { } while (0)

Functional macro to enable the cycle-counting capability of the core Data Watchpoint and Trace unit.

Note that this functionality is optional, so may not be present on your device. This is a no-op in that case.

Dependency:: BSPACM_CORE_SUPPORTS_CYCCNT

#define BSPACM_CORE_ENABLE_INTERRUPT ( ) __enable_irq()

Gratuitous alternative spelling of standard CMSIS core intrinsic.

#define BSPACM_CORE_INLINE __inline__

Mark a function to be inlined.

Most toolchains support this feature, but the spelling of the request varies.

The toolchain is free to ignore the request, which is after all only the developer's expert opinion. When optimizing for size toolchains are likely to ignore this if more than one call site is in the translation unit.

See also: BSPACM_CORE_INLINE_FORCED

#define BSPACM_CORE_INLINE_FORCED BSPACM_CORE_INLINE __attribute__((__always_inline__))

Insist that a function be inlined.

Use this when BSPACM_CORE_INLINE is being ignored. Not all toolchains will support this; on those it should be treated as BSPACM_CORE_INLINE.

#define BSPACM_CORE_PACKED_STRUCT ( nm_ ) struct __attribute__((__packed__)) nm_

Declare a packed structure in a toolchain-specific manner.

Parameters

nm_	name of the structure to be declared

This expands to struct nm_ annotated with toolchain-specific directives to ensure the structure contents have no padding. It is used for binary messages that mix types which might normally require padding to maintain MCU-standard alignment.

#define BSPACM_CORE_REENABLE_INTERRUPT ( var_ )

Value:

do { \
    if (! (1U & var_)) {                          \
      BSPACM_CORE_ENABLE_INTERRUPT();             \
    }                                             \
  } while (0)

If interrupts were enabled when var_ was declared (generally by BSPACM_CORE_SAVED_INTERRUPT_STATE()), then enable them; otherwise leave them in their current state.

#define BSPACM_CORE_RESTORE_INTERRUPT_STATE ( var_ )

Value:

do { \
    if (1U & var_) {                                   \
      BSPACM_CORE_DISABLE_INTERRUPT();                 \
    } else {                                           \
      BSPACM_CORE_ENABLE_INTERRUPT();                  \
    }                                                  \
  } while (0)

Restore the interrupt enable state to what it was when var_ was assigned. This will invoke either BSPACM_CORE_ENABLE_INTERRUPT() or BSPACM_CORE_DISABLE_INTERRUPT(). You may want BSPACM_CORE_REENABLE_INTERRUPT() instead.

#define BSPACM_CORE_SAVED_INTERRUPT_STATE ( var_ ) unsigned int const var_ = __get_PRIMASK()

Declare and initialize a const variable that records whether interrupts are disabled. The value is the PRIMASK register.

Note: This macro expands to a variable definition with an initializer expression, so must be placed in an appropriate context.

Parameters

var_	an identifier for a variable that will be defined to hold the value of the PRIMASK register at the point of definition.

#define BSPACM_CORE_SLEEP ( )

Value:

do { \
    __WFI();                     \
  } while(0)

Enter the Cortex-M sleep mode.

The specific effect of this is vendor-specific, but in concept it turns off the processor clock and leaves all other clocks running. The implementation may map to a vendor-specific function or macro, but is expected to be equivalent to invoking the ARM instruction WFI (or WFE) with the SLEEPDEEP bit of System Control Register clear.

Warning: The implementation of this operation is device-specific.

Note: The user should be aware of the effect of this operation on the hardware an application targets. Interrupts that cause wakeup will, if not masked through PRIMASK, be executed prior to control returning to the point following the __WFI() operation, meaning that any clocks disabled by the operation will not be restored until interrupt processing completes and control returns to the remainder of this macro.

See also: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/CHDJJHJI.html

#define BSPACM_CORE_SUPPORTS_CYCCNT 0

Defined to true value if cycle-counting is supported on the architecture. This is false on a Cortex-M0+ device.

#define BSPACM_VERSION 20150113

Version identifier for the BSPACM infrastructure

A monotonically non-decreasing integer reflecting the version of BSPACM that is being used. The value represents a development freeze date in the form YYYYMMDD as a decimal number.

Function Documentation

static BSPACM_CORE_INLINE unsigned int uiBSPACMcoreBitFromMask ( uint32_t mask )

static

Convert a bit mask to a bit number.

Useful for bitband object references. Some vendors (SiLabs) provide macros for bit positions; some (TI) only provide the mask values.

Warning: If the passed value does not have exactly one bit set, this function will hang.

Parameters

mask	a bit mask. Exactly one bit must be set. In normal use the parameter is a compile-time constant so this function reduces to a compile-time constant too.

Returns: the offset of the single set bit in mask.

static BSPACM_CORE_INLINE void vBSPACMcoreSetPinNybble	(	volatile uint32_t *	basep,
		unsigned int	pin,
		unsigned int	value
	)

static

Function to set the value of a nybble in a word array.

This is the API for things like GPIO pin alternative function selection and interrupt source port selection on the EFM32, and DMA channel source selection on the TM4C.

Parameters

regp	pointer to a consecutive sequence of one or more words that hold packed nybble values. Each word holds eight nybbles.
pin	the pin number is the ordinal of the nybble to be set.
value	the nybble value to be stored. Only the four low bits are used.

Macros

Functions

Detailed Description

Macro Definition Documentation

Function Documentation