core.h

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/* Copyright 2014, Peter A. Bigot
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * * Neither the name of the software nor the names of its contributors may be
 *   used to endorse or promote products derived from this software without
 *   specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef BSPACM_CORE_H
#define BSPACM_CORE_H

#if (__cplusplus - 0)
#include <cstdint>
#include <cstddef>
#else /* __cplusplus */
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#endif /* __cplusplus */

#if defined(BSPACM_DOXYGEN) || (BSPACM_CORE_TOOLCHAIN_GCC - 0)
#define BSPACM_CORE_INLINE __inline__
#else /* TOOLCHAIN */
#define BSPACM_CORE_INLINE inline
#endif /* TOOLCHAIN */

#if defined(BSPACM_DOXYGEN) || (BSPACM_CORE_TOOLCHAIN_GCC - 0)
/* GCC wants both directives */
#define BSPACM_CORE_INLINE_FORCED BSPACM_CORE_INLINE __attribute__((__always_inline__))
#else /* TOOLCHAIN */
#define BSPACM_CORE_INLINE_FORCED BSPACM_CORE_INLINE
#endif /* TOOLCHAIN */

#if defined(BSPACM_DOXYGEN) || (BSPACM_CORE_TOOLCHAIN_GCC - 0)
#define BSPACM_CORE_PACKED_STRUCT(nm_) struct __attribute__((__packed__)) nm_
#endif /* TOOLCHAIN */

#if defined(BSPACM_DOXYGEN) || (BSPACM_CORE_TOOLCHAIN_GCC - 0)
#define BSPACM_CORE_ALIGNED_OBJECT(sz_) __attribute__((__aligned__(sz_)))
#endif /* TOOLCHAIN */

/* Device-specific material.  This includes device vendor and CMSIS
 * headers, and provides any necessary bridging declarations.  The
 * correct content should be located by the prioritization of include
 * paths, but is generally found in the device/SERIES include
 * hierarchy. */
#include <bspacm/device.h>

/* Application/board-specific material.  This corresponds to the
 * material in @c periph_config.c, and has things such as the handle
 * to the default system UART peripheral.  A default is provided in
 * each board-specific include hierarchy, but it can be overridden by
 * providing a path to another file in the providing a higher-priority
 * path in the application-specific Makefile. */
#include <bspacm/config.h>

#define BSPACM_VERSION 20150113

#define BSPACM_CORE_DISABLE_INTERRUPT() __disable_irq()

#define BSPACM_CORE_ENABLE_INTERRUPT() __enable_irq()

#define BSPACM_CORE_SAVED_INTERRUPT_STATE(var_) unsigned int const var_ = __get_PRIMASK()

#define BSPACM_CORE_RESTORE_INTERRUPT_STATE(var_) do { \
    if (1U & var_) {                                   \
      BSPACM_CORE_DISABLE_INTERRUPT();                 \
    } else {                                           \
      BSPACM_CORE_ENABLE_INTERRUPT();                  \
    }                                                  \
  } while (0)

#define BSPACM_CORE_REENABLE_INTERRUPT(var_) do { \
    if (! (1U & var_)) {                          \
      BSPACM_CORE_ENABLE_INTERRUPT();             \
    }                                             \
  } while (0)

#if defined(BSPACM_DOXYGEN) || (! defined(BSPACM_CORE_SLEEP))

#define BSPACM_CORE_SLEEP() do { \
    __WFI();                     \
  } while(0)
#endif /* BSPACM_CORE_SLEEP */

#if defined(BSPACM_DOXYGEN) || (! defined(BSPACM_CORE_DEEP_SLEEP))

#define BSPACM_CORE_DEEP_SLEEP() do {                           \
    uint32_t in_sleepdeep = (SCB->SCR & SCB_SCR_SLEEPDEEP_Msk); \
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;                          \
    __WFI();                                                    \
    SCB->SCR &= ~in_sleepdeep;                                  \
  } while(0)
#endif /* BSPACM_CORE_DEEP_SLEEP */

#if defined(DWT_CTRL_NOCYCCNT_Msk)
#define BSPACM_CORE_SUPPORTS_CYCCNT 1
#else /* DWT_CTRL_NOCYCCNT_Msk */
#define BSPACM_CORE_SUPPORTS_CYCCNT 0
#endif /* DWT_CTRL_NOCYCCNT_Msk */

#if (BSPACM_CORE_SUPPORTS_CYCCNT - 0)
#define BSPACM_CORE_ENABLE_CYCCNT() do {              \
    if (! (DWT_CTRL_NOCYCCNT_Msk & DWT->CTRL)) {      \
      CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; \
      DWT->CYCCNT = 0;                                \
      DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;            \
    }                                                 \
  } while (0)
#else /* BSPACM_CORE_SUPPORTS_CYCCNT */
#define BSPACM_CORE_ENABLE_CYCCNT() do { } while (0)
#endif /* BSPACM_CORE_SUPPORTS_CYCCNT */

#if (BSPACM_CORE_SUPPORTS_CYCCNT - 0)
#define BSPACM_CORE_DISABLE_CYCCNT() do {              \
    if (! (DWT_CTRL_NOCYCCNT_Msk & DWT->CTRL)) {       \
      DWT->CTRL &= ~DWT_CTRL_CYCCNTENA_Msk;            \
      CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; \
    }                                                  \
  } while (0)
#else /* BSPACM_CORE_SUPPORTS_CYCCNT */
#define BSPACM_CORE_DISABLE_CYCCNT() do { } while (0)
#endif /* BSPACM_CORE_SUPPORTS_CYCCNT */

#if (BSPACM_CORE_SUPPORTS_CYCCNT - 0)
#define BSPACM_CORE_CYCCNT() DWT->CYCCNT
#else /* BSPACM_CORE_SUPPORTS_CYCCNT */
#define BSPACM_CORE_CYCCNT() 0
#endif /* BSPACM_CORE_SUPPORTS_CYCCNT */

#if (BSPACM_CORE_SUPPORTS_CYCCNT - 0)
#define BSPACM_CORE_DELAY_CYCLES(cycles_) do {  \
    uint32_t const delta = (cycles_);           \
    uint32_t const cc0 = DWT->CYCCNT;           \
    while ((DWT->CYCCNT - cc0) < delta) {       \
      /* spin */                                \
    }                                           \
  } while (0)
#else /* BSPACM_CORE_SUPPORTS_CYCCNT */
#define BSPACM_CORE_DELAY_CYCLES(cycles_) do {  \
    uint32_t const cycles_per_iter = 3;         \
    uint32_t remaining = (cycles_);             \
    while (remaining > cycles_per_iter) {       \
      remaining -= cycles_per_iter;             \
    }                                           \
  } while (0)
#endif /* BSPACM_CORE_SUPPORTS_CYCCNT */

/* Cortex-M3 devices support bit-band access to SRAM and peripherals,
 * but Cortex-M0+ does not, so the following features are optional. */

#if defined(BSPACM_DOXYGEN) || (defined(BSPACM_CORE_SRAM_BASE) && defined(BSPACM_CORE_SRAM_BITBAND_BASE))
/* @cond DOXYGEN_EXCLUDE */
#define BSPACM_CORE_BITBAND_SRAM_(object_, bit_) (BSPACM_CORE_SRAM_BITBAND_BASE + 4 * ((bit_) + 8 * ((uintptr_t)&(object_) - BSPACM_CORE_SRAM_BASE)))
/* @endcond */

#define BSPACM_CORE_BITBAND_SRAM32(object_, bit_) (*(volatile uint32_t *)BSPACM_CORE_BITBAND_SRAM_(object_, bit_))

#define BSPACM_CORE_BITBAND_SRAM16(object_, bit_) (*(volatile uint16_t *)BSPACM_CORE_BITBAND_SRAM_(object_, bit_))

#define BSPACM_CORE_BITBAND_SRAM8(object_, bit_) (*(volatile uint8_t *)BSPACM_CORE_BITBAND_SRAM_(object_, bit_))

#endif /* SRAM bitband supported */

#if defined(BSPACM_DOXYGEN) || (defined(BSPACM_CORE_PERIPH_BASE) && defined(BSPACM_CORE_PERIPH_BITBAND_BASE))

#define BSPACM_CORE_BITBAND_PERIPH(object_, bit_) (*(volatile uint32_t *)(BSPACM_CORE_PERIPH_BITBAND_BASE + 4 * ((bit_) + 8 * ((uintptr_t)&(object_) - BSPACM_CORE_PERIPH_BASE))))
#endif /* PERIPH bitband supported */

static BSPACM_CORE_INLINE
unsigned int
uiBSPACMcoreBitFromMask (uint32_t mask)
{
  if (0x1U == mask) {
    return 0;
  } else  if (0x2U == mask) {
    return 1;
  } else  if (0x4U == mask) {
    return 2;
  } else  if (0x8U == mask) {
    return 3;
  } else  if (0x10U == mask) {
    return 4;
  } else  if (0x20U == mask) {
    return 5;
  } else  if (0x40U == mask) {
    return 6;
  } else  if (0x80U == mask) {
    return 7;
  } else  if (0x100U == mask) {
    return 8;
  } else  if (0x200U == mask) {
    return 9;
  } else  if (0x400U == mask) {
    return 10;
  } else  if (0x800U == mask) {
    return 11;
  } else  if (0x1000U == mask) {
    return 12;
  } else  if (0x2000U == mask) {
    return 13;
  } else  if (0x4000U == mask) {
    return 14;
  } else  if (0x8000U == mask) {
    return 15;
  } else  if (0x10000U == mask) {
    return 16;
  } else  if (0x20000U == mask) {
    return 17;
  } else  if (0x40000U == mask) {
    return 18;
  } else  if (0x80000U == mask) {
    return 19;
  } else  if (0x100000U == mask) {
    return 20;
  } else  if (0x200000U == mask) {
    return 21;
  } else  if (0x400000U == mask) {
    return 22;
  } else  if (0x800000U == mask) {
    return 23;
  } else  if (0x1000000U == mask) {
    return 24;
  } else  if (0x2000000U == mask) {
    return 25;
  } else  if (0x4000000U == mask) {
    return 26;
  } else  if (0x8000000U == mask) {
    return 27;
  } else  if (0x10000000U == mask) {
    return 28;
  } else  if (0x20000000U == mask) {
    return 29;
  } else  if (0x40000000U == mask) {
    return 30;
  } else  if (0x80000000U != mask) {
    /* Not exactly one bit set.  This is an error in usage. */
    while(1);
  }
  return 31;
}

static BSPACM_CORE_INLINE
void vBSPACMcoreSetPinNybble (volatile uint32_t * basep,
                              unsigned int pin,
                              unsigned int value)
{
  volatile uint32_t * const wordp = basep + (pin / 8);
  const unsigned int shift = 4 * (pin % 8);
  *wordp = (*wordp & ~(0x0F << shift)) | ((0x0F & value) << shift);
}

#endif /* BSPACM_CORE_H */