BSP430  20141115
Board Support Package for MSP430 microcontrollers
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port.h
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1 /* Copyright 2012-2014, Peter A. Bigot
2  *
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * * Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * * Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * * Neither the name of the software nor the names of its contributors may be
16  * used to endorse or promote products derived from this software without
17  * specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
113 /* !BSP430! periph=port */
114 /* !BSP430! instance=PORT1,PORT2,PORT3,PORT4,PORT5,PORT6,PORT7,PORT8,PORT9,PORT10,PORT11 */
115 
116 #ifndef BSP430_PERIPH_PORT_H
117 #define BSP430_PERIPH_PORT_H
118 
119 #include <bsp430/periph.h>
120 
127 #define BSP430_MODULE_PORT (defined(__MSP430_HAS_PORT1__) \
128  || defined(__MSP430_HAS_PORT1_R__))
129 
130 #if defined(BSP430_DOXYGEN) || (BSP430_MODULE_PORT - 0)
131 
132 /* Analysis of port capabilities:
133  *
134  * 1xx: P1/P2 are uniform contiguous with interrupt capability. P3-P6
135  * are uniform contiguous without interrupt capability. There is no
136  * REN capability.
137  *
138  * 2xx: P1/P2 are uniform contiguous inclusive of REN but exclusive of
139  * SEL2, which is contiguous at a distinct base address, and have
140  * interrupt capability. P3-P6 are uniform 8-bit and P7-P8 are
141  * uniform 16-bit contiguous, exclusive of REN and SEL2. If any port
142  * has SEL2, all ports have SEL2. PA=(P7,P8) in the headers, but is
143  * not named as such in the user's guide.
144  *
145  * 3xx: P1/P2 are uniform contiguous with interrupt capability. P3-P4
146  * are uniform contiguous without interrupt capability. There is no
147  * REN capability.
148  *
149  * 4xx: P1/P2 are uniform contiguous including REN capability, and
150  * have interrupt capability. P3-P6 are uniform 8-bit and P7-P10 are
151  * uniform 16-bit contiguous; these are exclusive of REN, which is
152  * contiguous at a distinct base address. Some MCUs have SEL2 on P1,
153  * but no other ports have SEL2. PA=(P7,P8), PB=(P9,P10).
154  *
155  * 5xx: All ports uniform 16-bit contiguous. PA=(P1,P2), PB=(P3,P4),
156  * and so forth. All registers have space reserved for interrupt
157  * support. Only FR5XX has PxSELC.
158  *
159  * In the above, "8-bit" means that the register fields are
160  * immediately adjacent with byte addresses. "16-bit" means that
161  * register pairs are interleaved within function; e.g. P1IN would be
162  * at 0x00 while P2IN is at 0x01 and P1OUT at 0x02.
163  *
164  * 16-bit ports were introduced in MSP430X and are available on
165  * several chips in the 2xx and 4xx family. In 2xx/4xx MCUs, PORTA
166  * overlays P7/P8; in 5xx MCUs it overlays P1/P2.
167  *
168  * In pre-5xx families, registers supporting interrupts have a
169  * different layout than registers that do not support interrupts.
170  * However, the layouts (exclusive of SEL2 and REN) are compatible
171  * within those types.
172  *
173  * Thus there are several distinct layouts that need to be supported:
174  *
175  * + [PORT_IE_8] Pre-5xx interrupt-capable, 8-bit interface
176  * + [PORT_8] Pre-5xx non-interrupt, 8-bit interface
177  * + [PORT_16] Pre-5xx non-interrupt, 16-bit interface
178  * + [PORT_5XX] 5xx registers, 8-bit interface
179  * + [PORT_5XX_16] 5xx registers, 16-bit interface
180  *
181  * 5xx chips are identified by MSP430XV2_CPU. For these, a uniform
182  * HPL based on the 16-bit alphabetic register names is presented.
183  */
184 
198 #if defined(__MSP430_HAS_PORT1_R__)
199 #define BSP430_PORT_SUPPORTS_REN 1
200 #else /* P1REN */
201 #define BSP430_PORT_SUPPORTS_REN 0
202 #endif /* P1REN */
203 
208 #define BSP430_PORT_REN_HIGH_Z -1
209 
213 #define BSP430_PORT_REN_PULL_DOWN 0
214 
218 #define BSP430_PORT_REN_PULL_UP 1
219 
244 #if defined(BSP430_DOXYGEN) || (BSP430_PORT_SUPPORTS_REN - 0)
245 #define BSP430_PORT_HAL_SET_REN(hal_, bit_, rv_) do { \
246  if ((BSP430_PORT_REN_PULL_UP == (rv_)) \
247  || (BSP430_PORT_REN_PULL_DOWN == (rv_))) { \
248  if (BSP430_PORT_REN_PULL_UP == (rv_)) { \
249  BSP430_PORT_HAL_HPL_OUT(hal_) |= (bit_); \
250  } else { \
251  BSP430_PORT_HAL_HPL_OUT(hal_) &= ~(bit_); \
252  } \
253  BSP430_PORT_HAL_HPL_REN(hal_) |= (bit_); \
254  } else { \
255  BSP430_PORT_HAL_HPL_REN(hal_) &= ~(bit_); \
256  } \
257  } while (0)
258 #else /* BSP430_PORT_SUPPORTS_REN */
259 #define BSP430_PORT_HAL_SET_REN(hal_, bit_, rv_) do { } while (0)
260 #endif /* BSP430_PORT_SUPPORTS_REN */
261 
287 #if defined(BSP430_DOXYGEN) || (BSP430_PORT_SUPPORTS_REN - 0)
288 #define BSP430_PORT_HPL_SET_REN(hpl_, bit_, rv_) do { \
289  if ((BSP430_PORT_REN_PULL_UP == (rv_)) \
290  || (BSP430_PORT_REN_PULL_DOWN == (rv_))) { \
291  if (BSP430_PORT_REN_PULL_UP == (rv_)) { \
292  (hpl_)->out |= (bit_); \
293  } else { \
294  (hpl_)->out &= ~(bit_); \
295  } \
296  (hpl_)->ren |= (bit_); \
297  } else { \
298  (hpl_)->ren &= ~(bit_); \
299  } \
300  } while (0)
301 #else /* BSP430_PORT_SUPPORTS_REN */
302 #define BSP430_PORT_HPL_SET_REN(hal_, bit_, rv_) do { } while (0)
303 #endif /* BSP430_PORT_SUPPORTS_REN */
304 
314 #if defined(BSP430_DOXYGEN) || ! defined(BSP430_PORT_SUPPORTS_SEL2_2XX)
315 #define BSP430_PORT_SUPPORTS_SEL2_2XX ((! (BSP430_CORE_FAMILY_IS_5XX - 0)) \
316  && (defined(P1SEL2_) || defined(P1SEL)) \
317  && (defined(P2SEL2_) || defined(P2SEL2)))
318 #endif /* BSP430_PORT_SUPPORTS_SEL2_2XX */
319 
329 #if defined(BSP430_DOXYGEN) || ! defined(BSP430_PORT_SUPPORTS_SEL2_47XX)
330 #define BSP430_PORT_SUPPORTS_SEL2_47XX ((! (BSP430_CORE_FAMILY_IS_5XX - 0)) \
331  && (defined(P1SEL2_) || defined(P1SEL2)) \
332  && ! (defined(P2SEL2_) || defined(P2SEL2)))
333 #endif /* BSP430_PORT_SUPPORTS_SEL2_47XX */
334 
344 #if defined(BSP430_DOXYGEN) || ! defined(BSP430_PORT_SUPPORTS_SEL2_5XX)
345 #define BSP430_PORT_SUPPORTS_SEL2_5XX ((BSP430_CORE_FAMILY_IS_5XX - 0) \
346  && (defined(PASEL0_) || defined(PASEL0)) \
347  && ! (defined(PASELC_) || defined(PASELC)))
348 #endif /* BSP430_PORT_SUPPORTS_SEL2_5XX */
349 
358 #if defined(BSP430_DOXYGEN) || ! defined(BSP430_PORT_SUPPORTS_SEL2C_5XX)
359 #define BSP430_PORT_SUPPORTS_SEL2C_5XX ((BSP430_CORE_FAMILY_IS_5XX - 0) \
360  && (defined(PASEL0_) || defined(PASEL0)) \
361  && (defined(PASELC_) || defined(PASELC)))
362 #endif /* BSP430_PORT_SUPPORTS_SEL2C_5XX */
363 
366 #define BSP430_PORT_SUPPORTS_SEL2 ((BSP430_PORT_SUPPORTS_SEL2_2XX - 0) \
367  || (BSP430_PORT_SUPPORTS_SEL2_47XX - 0) \
368  || (BSP430_PORT_SUPPORTS_SEL2_5XX - 0) \
369  || (BSP430_PORT_SUPPORTS_SEL2C_5XX - 0))
370 
436 #if (BSP430_PORT_SUPPORTS_SEL2_2XX - 0)
437 #define BSP430_PORT_HPL_SET_SEL(hpl_, bit_, sel_) do { \
438  if (0x01 & (sel_)) { \
439  (hpl_)->sel |= (bit_); \
440  } else { \
441  (hpl_)->sel &= ~(bit_); \
442  } \
443  } while (0)
444 #define BSP430_PORT_HAL_SET_SEL(hal_, bit_, sel_) do { \
445  if (0x01 & (sel_)) { \
446  BSP430_PORT_HAL_HPL_SEL(hal_) |= (bit_); \
447  } else { \
448  BSP430_PORT_HAL_HPL_SEL(hal_) &= ~(bit_); \
449  } \
450  if (0x02 & (sel_)) { \
451  *(hal_)->sel2p |= (bit_); \
452  } else { \
453  *(hal_)->sel2p &= ~(bit_); \
454  } \
455  } while (0)
456 /* #elif (BSP430_PORT_SUPPORTS_SEL2_47XX - 0) : NOT SUPPORTED AT THIS TIME */
457 #elif (BSP430_PORT_SUPPORTS_SEL2_5XX - 0) || defined(BSP430_DOXYGEN)
458 #define BSP430_PORT_HPL_SET_SEL(hpl_, bit_, sel_) do { \
459  if (0x01 & (sel_)) { \
460  (hpl_)->sel |= (bit_); \
461  } else { \
462  (hpl_)->sel &= ~(bit_); \
463  } \
464  if (0x02 & (sel_)) { \
465  (hpl_)->sel1 |= (bit_); \
466  } else { \
467  (hpl_)->sel1 &= ~(bit_); \
468  } \
469  } while (0)
470 #define BSP430_PORT_HAL_SET_SEL(hal_, bit_, sel_) BSP430_PORT_HPL_SET_SEL((hal_)->hpl.port_5xx_8, bit_, sel_)
471 #elif (BSP430_PORT_SUPPORTS_SEL2C_5XX - 0)
472 /* Ugliness: if bits in both registers are to change, then use SELC.
473  * Otherwise only one actually changes, so it's ok to write both. */
474 #define BSP430_PORT_HPL_SET_SEL(hpl_, bit_, sel_) do { \
475  unsigned char cs = (((!!((bit_) & (hpl_)->sel1) != !!(0x02 & (sel_))) << 1) \
476  | (!!((bit_) & (hpl_)->sel0) != !!(0x01 & (sel_)))); \
477  if (0x03 == cs) { \
478  (hpl_)->selc |= (bit_); \
479  } else { \
480  if (0x01 & (sel_)) { \
481  (hpl_)->sel0 |= (bit_); \
482  } else { \
483  (hpl_)->sel0 &= ~(bit_); \
484  } \
485  if (0x02 & (sel_)) { \
486  (hpl_)->sel1 |= (bit_); \
487  } else { \
488  (hpl_)->sel1 &= ~(bit_); \
489  } \
490  } \
491  } while (0)
492 #define BSP430_PORT_HAL_SET_SEL(hal_, bit_, sel_) BSP430_PORT_HPL_SET_SEL((hal_)->hpl.port_5xx_8, bit_, sel_)
493 #else /* SEL2 options */
494 #define BSP430_PORT_HPL_SET_SEL(hpl_, bit_, sel_) do { \
495  if (0x01 & (sel_)) { \
496  (hpl_)->sel |= (bit_); \
497  } else { \
498  (hpl_)->sel &= ~(bit_); \
499  } \
500  } while (0)
501 #define BSP430_PORT_HAL_SET_SEL(hal_, bit_, sel_) do { \
502  if (0x01 & (sel_)) { \
503  BSP430_PORT_HAL_HPL_SEL(hal_) |= (bit_); \
504  } else { \
505  BSP430_PORT_HAL_HPL_SEL(hal_) &= ~(bit_); \
506  } \
507  } while (0)
508 #endif /* SEL2 options */
509 
514 typedef struct sBSP430hplPORT_IE_8 {
515  unsigned char in; /* 0x00 */
516  unsigned char out; /* 0x01 */
517  unsigned char dir; /* 0x02 */
518  unsigned char ifg; /* 0x03 */
519  unsigned char ies; /* 0x04 */
520  unsigned char ie; /* 0x05 */
521  unsigned char sel; /* 0x06 */
522  unsigned char ren; /* 0x07 */
524 
529 typedef struct sBSP430hplPORT_8 {
530  unsigned char in; /* 0x00 */
531  unsigned char out; /* 0x01 */
532  unsigned char dir; /* 0x02 */
533  unsigned char sel; /* 0x03 */
535 
537 typedef union uBSP430hplPORT_16 {
538  unsigned int w;
539  unsigned char b[2];
540  struct {
541  unsigned char l;
542  unsigned char h;
543  };
545 
550 typedef struct sBSP430hplPORT_16 {
551  uBSP430hplPORT_16 in; /* 0x00 */
552  uBSP430hplPORT_16 out; /* 0x02 */
553  uBSP430hplPORT_16 dir; /* 0x04 */
554  uBSP430hplPORT_16 sel; /* 0x08 */
556 
559 typedef struct sBSP430hplPORT_5XX_16 {
560  uBSP430hplPORT_16 in; /* 0x00 */
561  uBSP430hplPORT_16 out; /* 0x02 */
562  uBSP430hplPORT_16 dir; /* 0x04 */
563  uBSP430hplPORT_16 ren; /* 0x06 */
564  uBSP430hplPORT_16 ds; /* 0x08 */
565  union {
566  uBSP430hplPORT_16 sel; /* 0x0A */
568  };
570  unsigned int _reserved_x0E;
571  unsigned int _reserved_x10;
572  unsigned int _reserved_x12;
573  unsigned int _reserved_x14;
575  uBSP430hplPORT_16 ies; /* 0x18 */
576  uBSP430hplPORT_16 ie; /* 0x1A */
577  uBSP430hplPORT_16 ifg; /* 0x1C */
579 
585 typedef struct sBSP430hplPORT_5XX_8 {
586  unsigned char in; /* 0x00 */
587  unsigned char _reserved_x01;
588  unsigned char out; /* 0x02 */
589  unsigned char _reserved_x03;
590  unsigned char dir; /* 0x04 */
591  unsigned char _reserved_x05;
592  unsigned char ren; /* 0x06 */
593  unsigned char _reserved_x07;
594  unsigned char ds; /* 0x08 */
595  unsigned char _reserved_x09;
596  union __attribute__((__packed__))
597  {
598  unsigned char sel; /* 0x0A */
599  unsigned char sel0; /* 0x0A */
600  };
601  unsigned char _reserved_x0B;
602  unsigned char sel1; /* 0x0C */
603  unsigned char _reserved_x0D;
604  unsigned char _reserved_x0E;
605  unsigned char _reserved_x0F;
606  unsigned char _reserved_x10;
607  unsigned char _reserved_x11;
608  unsigned char _reserved_x12;
609  unsigned char _reserved_x13;
610  unsigned char _reserved_x14;
611  unsigned char _reserved_x15;
612  unsigned char selc; /* 0x16 */
613  unsigned char _reserved_x17;
614  unsigned char ies; /* 0x18 */
615  unsigned char _reserved_x19;
616  unsigned char ie; /* 0x1A */
617  unsigned char _reserved_x1B;
618  unsigned char ifg; /* 0x1C */
620 
624 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
626 #else /* 5XX */
628 #endif /* 5XX */
629 
633 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
635 #else /* 5XX */
637 #endif /* 5XX */
638 
642 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
644 #else /* 5XX */
646 #endif /* 5XX */
647 
650 /* Port address constants are not defined for use outside the BSP430
651  * implementation, but are used outside the port HPL and HAL feature.
652  * In particular these constants are used to simplify the
653  * implementation of iBSP430platformConfigurePeripheralPins_ni without
654  * requiring access to the "real" HPL handles for the peripheral
655  * ports. */
656 
657 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
658 /* All 5xx ports are resistor enabled */
659 #define BSP430_PERIPH_PORTA_BASEADDRESS_ __MSP430_BASEADDRESS_PORTA_R__
660 #define BSP430_PERIPH_PORTB_BASEADDRESS_ __MSP430_BASEADDRESS_PORTB_R__
661 #define BSP430_PERIPH_PORTC_BASEADDRESS_ __MSP430_BASEADDRESS_PORTC_R__
662 #define BSP430_PERIPH_PORTD_BASEADDRESS_ __MSP430_BASEADDRESS_PORTD_R__
663 #define BSP430_PERIPH_PORTE_BASEADDRESS_ __MSP430_BASEADDRESS_PORTE_R__
664 #define BSP430_PERIPH_PORTF_BASEADDRESS_ __MSP430_BASEADDRESS_PORTF_R__
665 
666 /* There are __MSP430_BASEADDRESS_PORT1_R__ and
667  * __MSP430_BASEADDRESS_PORT2_R__, but they have the same value. */
668 #define BSP430_PERIPH_PORT1_BASEADDRESS_ __MSP430_BASEADDRESS_PORTA_R__
669 #define BSP430_PERIPH_PORT2_BASEADDRESS_ (1+__MSP430_BASEADDRESS_PORTA_R__)
670 #define BSP430_PERIPH_PORT3_BASEADDRESS_ __MSP430_BASEADDRESS_PORTB_R__
671 #define BSP430_PERIPH_PORT4_BASEADDRESS_ (1+__MSP430_BASEADDRESS_PORTB_R__)
672 #define BSP430_PERIPH_PORT5_BASEADDRESS_ __MSP430_BASEADDRESS_PORTC_R__
673 #define BSP430_PERIPH_PORT6_BASEADDRESS_ (1+__MSP430_BASEADDRESS_PORTC_R__)
674 #define BSP430_PERIPH_PORT7_BASEADDRESS_ __MSP430_BASEADDRESS_PORTD_R__
675 #define BSP430_PERIPH_PORT8_BASEADDRESS_ (1+__MSP430_BASEADDRESS_PORTD_R__)
676 #define BSP430_PERIPH_PORT9_BASEADDRESS_ __MSP430_BASEADDRESS_PORTE_R__
677 #define BSP430_PERIPH_PORT10_BASEADDRESS_ (1+__MSP430_BASEADDRESS_PORTE_R__)
678 #define BSP430_PERIPH_PORT11_BASEADDRESS_ __MSP430_BASEADDRESS_PORTF_R__
679 
680 #define BSP430_PERIPH_PORTJ_BASEADDRESS_ __MSP430_BASEADDRESS_PORTJ_R__
681 
682 #else /* 5xx */
683 /* Port addresses are fixed for all pre-5xx families. */
684 #define BSP430_PERIPH_PORT1_BASEADDRESS_ 0x0020
685 #define BSP430_PERIPH_PORT2_BASEADDRESS_ 0x0028
686 #define BSP430_PERIPH_PORT3_BASEADDRESS_ 0x0018
687 #define BSP430_PERIPH_PORT4_BASEADDRESS_ 0x001C
688 #define BSP430_PERIPH_PORT5_BASEADDRESS_ 0x0030
689 #define BSP430_PERIPH_PORT6_BASEADDRESS_ 0x0034
690 
691 #define BSP430_PERIPH_PORTA_BASEADDRESS_ 0x0038
692 #define BSP430_PERIPH_PORT7_BASEADDRESS_ 0x0038
693 #define BSP430_PERIPH_PORT8_BASEADDRESS_ 0x0039
694 
695 #define BSP430_PERIPH_PORTB_BASEADDRESS_ 0x0008
696 #define BSP430_PERIPH_PORT9_BASEADDRESS_ 0x0008
697 #define BSP430_PERIPH_PORT10_BASEADDRESS_ 0x0009
698 
699 #endif /* 5xx */
700  /* DOXYGEN_INTERNAL */
702 
705 #define BSP430_PORT_HAL_HPL_VARIANT_PORT_IE_8 1
706 
709 #define BSP430_PORT_HAL_HPL_VARIANT_PORT_8 2
710 
713 #define BSP430_PORT_HAL_HPL_VARIANT_PORT_16 3
714 
717 #define BSP430_PORT_HAL_HPL_VARIANT_PORT_5XX_8 4
718 
721 #define BSP430_PORT_HAL_HPL_VARIANT_PORT_5XX_16 5
722 
729 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
730 #define BSP430_PORT_HAL_HPL_VARIANT_PORTIE BSP430_PORT_HAL_HPL_VARIANT_PORT_5XX_8
731 #else /* 5XX */
732 #define BSP430_PORT_HAL_HPL_VARIANT_PORTIE BSP430_PORT_HAL_HPL_VARIANT_PORT_IE_8
733 #endif /* 5XX */
734 
741 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
742 #define BSP430_PORT_HAL_HPL_VARIANT_PORT BSP430_PORT_HAL_HPL_VARIANT_PORT_5XX_8
743 #else /* 5XX */
744 #define BSP430_PORT_HAL_HPL_VARIANT_PORT BSP430_PORT_HAL_HPL_VARIANT_PORT_8
745 #endif /* 5XX */
746 
752 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
753 #define BSP430_PORT_HAL_HPL_VARIANT_PORTW BSP430_PORT_HAL_HPL_VARIANT_PORT_5XX_16
754 #else /* 5XX */
755 #define BSP430_PORT_HAL_HPL_VARIANT_PORTW BSP430_PORT_HAL_HPL_VARIANT_PORT_16
756 #endif /* 5XX */
757 
758 /* !BSP430! instance=port_ie_8,port_8,port_16,port_5xx_8,port_5xx_16,port,portie,portw */
759 /* !BSP430! insert=hal_variant_hpl_macro */
760 /* BEGIN AUTOMATICALLY GENERATED CODE---DO NOT MODIFY [hal_variant_hpl_macro] */
762 #define BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_IE_8(hal_) (BSP430_PORT_HAL_HPL_VARIANT_PORT_IE_8 == BSP430_PERIPH_HAL_STATE_CFLAGS_VARIANT(hal_))
763 
767 #define BSP430_PORT_HAL_GET_HPL_PORT_IE_8(hal_) ((BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_IE_8(hal_)) ? (hal_)->hpl.port_ie_8 : (void *)0)
768 
770 #define BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_8(hal_) (BSP430_PORT_HAL_HPL_VARIANT_PORT_8 == BSP430_PERIPH_HAL_STATE_CFLAGS_VARIANT(hal_))
771 
775 #define BSP430_PORT_HAL_GET_HPL_PORT_8(hal_) ((BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_8(hal_)) ? (hal_)->hpl.port_8 : (void *)0)
776 
778 #define BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_16(hal_) (BSP430_PORT_HAL_HPL_VARIANT_PORT_16 == BSP430_PERIPH_HAL_STATE_CFLAGS_VARIANT(hal_))
779 
783 #define BSP430_PORT_HAL_GET_HPL_PORT_16(hal_) ((BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_16(hal_)) ? (hal_)->hpl.port_16 : (void *)0)
784 
786 #define BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_5XX_8(hal_) (BSP430_PORT_HAL_HPL_VARIANT_PORT_5XX_8 == BSP430_PERIPH_HAL_STATE_CFLAGS_VARIANT(hal_))
787 
791 #define BSP430_PORT_HAL_GET_HPL_PORT_5XX_8(hal_) ((BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_5XX_8(hal_)) ? (hal_)->hpl.port_5xx_8 : (void *)0)
792 
794 #define BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_5XX_16(hal_) (BSP430_PORT_HAL_HPL_VARIANT_PORT_5XX_16 == BSP430_PERIPH_HAL_STATE_CFLAGS_VARIANT(hal_))
795 
799 #define BSP430_PORT_HAL_GET_HPL_PORT_5XX_16(hal_) ((BSP430_PORT_HAL_HPL_VARIANT_IS_PORT_5XX_16(hal_)) ? (hal_)->hpl.port_5xx_16 : (void *)0)
800 
802 #define BSP430_PORT_HAL_HPL_VARIANT_IS_PORT(hal_) (BSP430_PORT_HAL_HPL_VARIANT_PORT == BSP430_PERIPH_HAL_STATE_CFLAGS_VARIANT(hal_))
803 
807 #define BSP430_PORT_HAL_GET_HPL_PORT(hal_) ((BSP430_PORT_HAL_HPL_VARIANT_IS_PORT(hal_)) ? (hal_)->hpl.port : (void *)0)
808 
810 #define BSP430_PORT_HAL_HPL_VARIANT_IS_PORTIE(hal_) (BSP430_PORT_HAL_HPL_VARIANT_PORTIE == BSP430_PERIPH_HAL_STATE_CFLAGS_VARIANT(hal_))
811 
815 #define BSP430_PORT_HAL_GET_HPL_PORTIE(hal_) ((BSP430_PORT_HAL_HPL_VARIANT_IS_PORTIE(hal_)) ? (hal_)->hpl.portie : (void *)0)
816 
818 #define BSP430_PORT_HAL_HPL_VARIANT_IS_PORTW(hal_) (BSP430_PORT_HAL_HPL_VARIANT_PORTW == BSP430_PERIPH_HAL_STATE_CFLAGS_VARIANT(hal_))
819 
823 #define BSP430_PORT_HAL_GET_HPL_PORTW(hal_) ((BSP430_PORT_HAL_HPL_VARIANT_IS_PORTW(hal_)) ? (hal_)->hpl.portw : (void *)0)
824 
825 /* END AUTOMATICALLY GENERATED CODE [hal_variant_hpl_macro] */
826 /* !BSP430! end=hal_variant_hpl_macro */
827 /* !BSP430! instance=PORT1,PORT2,PORT3,PORT4,PORT5,PORT6,PORT7,PORT8,PORT9,PORT10,PORT11 */
828 
834 #define BSP430_PORT_HAL_GET_PERIPH_HANDLE(hal_) xBSP430periphFromHPL((hal_)->hpl.any)
835 
838 typedef struct sBSP430halPORT {
849  union {
851  volatile void * any;
865  volatile sBSP430hplPORT * port;
867  volatile sBSP430hplPORTW * portw;
868  } const hpl;
871  const struct sBSP430halISRIndexedChainNode * volatile pin_cbchain_ni[8];
872 #if defined(BSP430_DOXYGEN) || ((BSP430_PORT_SUPPORTS_REN - 0) && ! (BSP430_CORE_FAMILY_IS_5XX - 0))
873 
880  volatile unsigned char * const renp;
881 #endif /* Pre-5xx REN */
882 #if defined(BSP430_DOXYGEN) || (BSP430_PORT_SUPPORTS_SEL2_2XX - 0)
883 
890  volatile unsigned char * const sel2p;
891 #endif /* Pre-5xx SEL2 */
893 
896 
898 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
899 #define BSP430_PORT_HAL_HPL_IN(hal_) ((hal_)->hpl.portie->in)
900 #else /* 5XX */
901 #define BSP430_PORT_HAL_HPL_IN(hal_) (*(BSP430_PORT_HAL_HPL_VARIANT_IS_PORTIE(hal_) ? &BSP430_PORT_HAL_GET_HPL_PORTIE(hal_)->in : &BSP430_PORT_HAL_GET_HPL_PORT(hal_)->in))
902 #endif /* 5XX */
903 
904 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
905 #define BSP430_PORT_HAL_HPL_OUT(hal_) ((hal_)->hpl.portie->out)
906 #else /* 5XX */
907 #define BSP430_PORT_HAL_HPL_OUT(hal_) (*(BSP430_PORT_HAL_HPL_VARIANT_IS_PORTIE(hal_) ? &BSP430_PORT_HAL_GET_HPL_PORTIE(hal_)->out : &BSP430_PORT_HAL_GET_HPL_PORT(hal_)->out))
908 #endif /* 5XX */
909 
910 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
911 #define BSP430_PORT_HAL_HPL_DIR(hal_) ((hal_)->hpl.portie->dir)
912 #else /* 5XX */
913 #define BSP430_PORT_HAL_HPL_DIR(hal_) (*(BSP430_PORT_HAL_HPL_VARIANT_IS_PORTIE(hal_) ? &BSP430_PORT_HAL_GET_HPL_PORTIE(hal_)->dir : &BSP430_PORT_HAL_GET_HPL_PORT(hal_)->dir))
914 #endif /* 5XX */
915 
916 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
917 #define BSP430_PORT_HAL_HPL_SEL(hal_) ((hal_)->hpl.portie->sel)
918 #else /* 5XX */
919 #define BSP430_PORT_HAL_HPL_SEL(hal_) (*(BSP430_PORT_HAL_HPL_VARIANT_IS_PORTIE(hal_) ? &BSP430_PORT_HAL_GET_HPL_PORTIE(hal_)->sel : &BSP430_PORT_HAL_GET_HPL_PORT(hal_)->sel))
920 #endif /* 5XX */
921 
924 #if defined(BSP430_DOXYGEN) || (BSP430_PORT_SUPPORTS_REN - 0)
925 #if (BSP430_CORE_FAMILY_IS_5XX - 0)
926 #define BSP430_PORT_HAL_HPL_REN(hal_) ((hal_)->hpl.portie->ren)
927 #else /* 5XX */
928 #define BSP430_PORT_HAL_HPL_REN(hal_) (*(hal_)->renp)
929 #endif /* 5XX */
930 #endif /* REN support */
931 
932 /* !BSP430! insert=hal_decl */
933 /* BEGIN AUTOMATICALLY GENERATED CODE---DO NOT MODIFY [hal_decl] */
950 #ifndef configBSP430_HAL_PORT1
951 #define configBSP430_HAL_PORT1 0
952 #endif /* configBSP430_HAL_PORT1 */
953 
955 #if (configBSP430_HAL_PORT1 - 0)
956 /* You do not need to know about this */
957 extern sBSP430halPORT xBSP430hal_PORT1_;
958 #endif /* configBSP430_HAL_PORT1 */
959 
967 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT1 - 0)
968 #define BSP430_HAL_PORT1 (&xBSP430hal_PORT1_)
969 #endif /* configBSP430_HAL_PORT1 */
970 
987 #ifndef configBSP430_HAL_PORT2
988 #define configBSP430_HAL_PORT2 0
989 #endif /* configBSP430_HAL_PORT2 */
990 
992 #if (configBSP430_HAL_PORT2 - 0)
993 /* You do not need to know about this */
994 extern sBSP430halPORT xBSP430hal_PORT2_;
995 #endif /* configBSP430_HAL_PORT2 */
996 
1004 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT2 - 0)
1005 #define BSP430_HAL_PORT2 (&xBSP430hal_PORT2_)
1006 #endif /* configBSP430_HAL_PORT2 */
1007 
1024 #ifndef configBSP430_HAL_PORT3
1025 #define configBSP430_HAL_PORT3 0
1026 #endif /* configBSP430_HAL_PORT3 */
1027 
1029 #if (configBSP430_HAL_PORT3 - 0)
1030 /* You do not need to know about this */
1031 extern sBSP430halPORT xBSP430hal_PORT3_;
1032 #endif /* configBSP430_HAL_PORT3 */
1033 
1041 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT3 - 0)
1042 #define BSP430_HAL_PORT3 (&xBSP430hal_PORT3_)
1043 #endif /* configBSP430_HAL_PORT3 */
1044 
1061 #ifndef configBSP430_HAL_PORT4
1062 #define configBSP430_HAL_PORT4 0
1063 #endif /* configBSP430_HAL_PORT4 */
1064 
1066 #if (configBSP430_HAL_PORT4 - 0)
1067 /* You do not need to know about this */
1068 extern sBSP430halPORT xBSP430hal_PORT4_;
1069 #endif /* configBSP430_HAL_PORT4 */
1070 
1078 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT4 - 0)
1079 #define BSP430_HAL_PORT4 (&xBSP430hal_PORT4_)
1080 #endif /* configBSP430_HAL_PORT4 */
1081 
1098 #ifndef configBSP430_HAL_PORT5
1099 #define configBSP430_HAL_PORT5 0
1100 #endif /* configBSP430_HAL_PORT5 */
1101 
1103 #if (configBSP430_HAL_PORT5 - 0)
1104 /* You do not need to know about this */
1105 extern sBSP430halPORT xBSP430hal_PORT5_;
1106 #endif /* configBSP430_HAL_PORT5 */
1107 
1115 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT5 - 0)
1116 #define BSP430_HAL_PORT5 (&xBSP430hal_PORT5_)
1117 #endif /* configBSP430_HAL_PORT5 */
1118 
1135 #ifndef configBSP430_HAL_PORT6
1136 #define configBSP430_HAL_PORT6 0
1137 #endif /* configBSP430_HAL_PORT6 */
1138 
1140 #if (configBSP430_HAL_PORT6 - 0)
1141 /* You do not need to know about this */
1142 extern sBSP430halPORT xBSP430hal_PORT6_;
1143 #endif /* configBSP430_HAL_PORT6 */
1144 
1152 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT6 - 0)
1153 #define BSP430_HAL_PORT6 (&xBSP430hal_PORT6_)
1154 #endif /* configBSP430_HAL_PORT6 */
1155 
1172 #ifndef configBSP430_HAL_PORT7
1173 #define configBSP430_HAL_PORT7 0
1174 #endif /* configBSP430_HAL_PORT7 */
1175 
1177 #if (configBSP430_HAL_PORT7 - 0)
1178 /* You do not need to know about this */
1179 extern sBSP430halPORT xBSP430hal_PORT7_;
1180 #endif /* configBSP430_HAL_PORT7 */
1181 
1189 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT7 - 0)
1190 #define BSP430_HAL_PORT7 (&xBSP430hal_PORT7_)
1191 #endif /* configBSP430_HAL_PORT7 */
1192 
1209 #ifndef configBSP430_HAL_PORT8
1210 #define configBSP430_HAL_PORT8 0
1211 #endif /* configBSP430_HAL_PORT8 */
1212 
1214 #if (configBSP430_HAL_PORT8 - 0)
1215 /* You do not need to know about this */
1216 extern sBSP430halPORT xBSP430hal_PORT8_;
1217 #endif /* configBSP430_HAL_PORT8 */
1218 
1226 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT8 - 0)
1227 #define BSP430_HAL_PORT8 (&xBSP430hal_PORT8_)
1228 #endif /* configBSP430_HAL_PORT8 */
1229 
1246 #ifndef configBSP430_HAL_PORT9
1247 #define configBSP430_HAL_PORT9 0
1248 #endif /* configBSP430_HAL_PORT9 */
1249 
1251 #if (configBSP430_HAL_PORT9 - 0)
1252 /* You do not need to know about this */
1253 extern sBSP430halPORT xBSP430hal_PORT9_;
1254 #endif /* configBSP430_HAL_PORT9 */
1255 
1263 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT9 - 0)
1264 #define BSP430_HAL_PORT9 (&xBSP430hal_PORT9_)
1265 #endif /* configBSP430_HAL_PORT9 */
1266 
1283 #ifndef configBSP430_HAL_PORT10
1284 #define configBSP430_HAL_PORT10 0
1285 #endif /* configBSP430_HAL_PORT10 */
1286 
1288 #if (configBSP430_HAL_PORT10 - 0)
1289 /* You do not need to know about this */
1290 extern sBSP430halPORT xBSP430hal_PORT10_;
1291 #endif /* configBSP430_HAL_PORT10 */
1292 
1300 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT10 - 0)
1301 #define BSP430_HAL_PORT10 (&xBSP430hal_PORT10_)
1302 #endif /* configBSP430_HAL_PORT10 */
1303 
1320 #ifndef configBSP430_HAL_PORT11
1321 #define configBSP430_HAL_PORT11 0
1322 #endif /* configBSP430_HAL_PORT11 */
1323 
1325 #if (configBSP430_HAL_PORT11 - 0)
1326 /* You do not need to know about this */
1327 extern sBSP430halPORT xBSP430hal_PORT11_;
1328 #endif /* configBSP430_HAL_PORT11 */
1329 
1337 #if defined(BSP430_DOXYGEN) || (configBSP430_HAL_PORT11 - 0)
1338 #define BSP430_HAL_PORT11 (&xBSP430hal_PORT11_)
1339 #endif /* configBSP430_HAL_PORT11 */
1340 
1341 /* END AUTOMATICALLY GENERATED CODE [hal_decl] */
1342 /* !BSP430! end=hal_decl */
1343 
1344 /* !BSP430! insert=periph_decl */
1345 /* BEGIN AUTOMATICALLY GENERATED CODE---DO NOT MODIFY [periph_decl] */
1361 #ifndef configBSP430_HPL_PORT1
1362 #define configBSP430_HPL_PORT1 (configBSP430_HAL_PORT1 - 0)
1363 #endif /* configBSP430_HPL_PORT1 */
1364 
1365 #if (configBSP430_HAL_PORT1 - 0) && ! (configBSP430_HPL_PORT1 - 0)
1366 #warning configBSP430_HAL_PORT1 requested without configBSP430_HPL_PORT1
1367 #endif /* HAL and not HPL */
1368 
1375 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT1 - 0)
1376 #define BSP430_PERIPH_PORT1 ((tBSP430periphHandle)(BSP430_PERIPH_PORT1_BASEADDRESS_))
1377 #endif /* configBSP430_HPL_PORT1 */
1378 
1394 #ifndef configBSP430_HPL_PORT2
1395 #define configBSP430_HPL_PORT2 (configBSP430_HAL_PORT2 - 0)
1396 #endif /* configBSP430_HPL_PORT2 */
1397 
1398 #if (configBSP430_HAL_PORT2 - 0) && ! (configBSP430_HPL_PORT2 - 0)
1399 #warning configBSP430_HAL_PORT2 requested without configBSP430_HPL_PORT2
1400 #endif /* HAL and not HPL */
1401 
1408 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT2 - 0)
1409 #define BSP430_PERIPH_PORT2 ((tBSP430periphHandle)(BSP430_PERIPH_PORT2_BASEADDRESS_))
1410 #endif /* configBSP430_HPL_PORT2 */
1411 
1427 #ifndef configBSP430_HPL_PORT3
1428 #define configBSP430_HPL_PORT3 (configBSP430_HAL_PORT3 - 0)
1429 #endif /* configBSP430_HPL_PORT3 */
1430 
1431 #if (configBSP430_HAL_PORT3 - 0) && ! (configBSP430_HPL_PORT3 - 0)
1432 #warning configBSP430_HAL_PORT3 requested without configBSP430_HPL_PORT3
1433 #endif /* HAL and not HPL */
1434 
1441 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT3 - 0)
1442 #define BSP430_PERIPH_PORT3 ((tBSP430periphHandle)(BSP430_PERIPH_PORT3_BASEADDRESS_))
1443 #endif /* configBSP430_HPL_PORT3 */
1444 
1460 #ifndef configBSP430_HPL_PORT4
1461 #define configBSP430_HPL_PORT4 (configBSP430_HAL_PORT4 - 0)
1462 #endif /* configBSP430_HPL_PORT4 */
1463 
1464 #if (configBSP430_HAL_PORT4 - 0) && ! (configBSP430_HPL_PORT4 - 0)
1465 #warning configBSP430_HAL_PORT4 requested without configBSP430_HPL_PORT4
1466 #endif /* HAL and not HPL */
1467 
1474 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT4 - 0)
1475 #define BSP430_PERIPH_PORT4 ((tBSP430periphHandle)(BSP430_PERIPH_PORT4_BASEADDRESS_))
1476 #endif /* configBSP430_HPL_PORT4 */
1477 
1493 #ifndef configBSP430_HPL_PORT5
1494 #define configBSP430_HPL_PORT5 (configBSP430_HAL_PORT5 - 0)
1495 #endif /* configBSP430_HPL_PORT5 */
1496 
1497 #if (configBSP430_HAL_PORT5 - 0) && ! (configBSP430_HPL_PORT5 - 0)
1498 #warning configBSP430_HAL_PORT5 requested without configBSP430_HPL_PORT5
1499 #endif /* HAL and not HPL */
1500 
1507 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT5 - 0)
1508 #define BSP430_PERIPH_PORT5 ((tBSP430periphHandle)(BSP430_PERIPH_PORT5_BASEADDRESS_))
1509 #endif /* configBSP430_HPL_PORT5 */
1510 
1526 #ifndef configBSP430_HPL_PORT6
1527 #define configBSP430_HPL_PORT6 (configBSP430_HAL_PORT6 - 0)
1528 #endif /* configBSP430_HPL_PORT6 */
1529 
1530 #if (configBSP430_HAL_PORT6 - 0) && ! (configBSP430_HPL_PORT6 - 0)
1531 #warning configBSP430_HAL_PORT6 requested without configBSP430_HPL_PORT6
1532 #endif /* HAL and not HPL */
1533 
1540 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT6 - 0)
1541 #define BSP430_PERIPH_PORT6 ((tBSP430periphHandle)(BSP430_PERIPH_PORT6_BASEADDRESS_))
1542 #endif /* configBSP430_HPL_PORT6 */
1543 
1559 #ifndef configBSP430_HPL_PORT7
1560 #define configBSP430_HPL_PORT7 (configBSP430_HAL_PORT7 - 0)
1561 #endif /* configBSP430_HPL_PORT7 */
1562 
1563 #if (configBSP430_HAL_PORT7 - 0) && ! (configBSP430_HPL_PORT7 - 0)
1564 #warning configBSP430_HAL_PORT7 requested without configBSP430_HPL_PORT7
1565 #endif /* HAL and not HPL */
1566 
1573 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT7 - 0)
1574 #define BSP430_PERIPH_PORT7 ((tBSP430periphHandle)(BSP430_PERIPH_PORT7_BASEADDRESS_))
1575 #endif /* configBSP430_HPL_PORT7 */
1576 
1592 #ifndef configBSP430_HPL_PORT8
1593 #define configBSP430_HPL_PORT8 (configBSP430_HAL_PORT8 - 0)
1594 #endif /* configBSP430_HPL_PORT8 */
1595 
1596 #if (configBSP430_HAL_PORT8 - 0) && ! (configBSP430_HPL_PORT8 - 0)
1597 #warning configBSP430_HAL_PORT8 requested without configBSP430_HPL_PORT8
1598 #endif /* HAL and not HPL */
1599 
1606 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT8 - 0)
1607 #define BSP430_PERIPH_PORT8 ((tBSP430periphHandle)(BSP430_PERIPH_PORT8_BASEADDRESS_))
1608 #endif /* configBSP430_HPL_PORT8 */
1609 
1625 #ifndef configBSP430_HPL_PORT9
1626 #define configBSP430_HPL_PORT9 (configBSP430_HAL_PORT9 - 0)
1627 #endif /* configBSP430_HPL_PORT9 */
1628 
1629 #if (configBSP430_HAL_PORT9 - 0) && ! (configBSP430_HPL_PORT9 - 0)
1630 #warning configBSP430_HAL_PORT9 requested without configBSP430_HPL_PORT9
1631 #endif /* HAL and not HPL */
1632 
1639 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT9 - 0)
1640 #define BSP430_PERIPH_PORT9 ((tBSP430periphHandle)(BSP430_PERIPH_PORT9_BASEADDRESS_))
1641 #endif /* configBSP430_HPL_PORT9 */
1642 
1658 #ifndef configBSP430_HPL_PORT10
1659 #define configBSP430_HPL_PORT10 (configBSP430_HAL_PORT10 - 0)
1660 #endif /* configBSP430_HPL_PORT10 */
1661 
1662 #if (configBSP430_HAL_PORT10 - 0) && ! (configBSP430_HPL_PORT10 - 0)
1663 #warning configBSP430_HAL_PORT10 requested without configBSP430_HPL_PORT10
1664 #endif /* HAL and not HPL */
1665 
1672 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT10 - 0)
1673 #define BSP430_PERIPH_PORT10 ((tBSP430periphHandle)(BSP430_PERIPH_PORT10_BASEADDRESS_))
1674 #endif /* configBSP430_HPL_PORT10 */
1675 
1691 #ifndef configBSP430_HPL_PORT11
1692 #define configBSP430_HPL_PORT11 (configBSP430_HAL_PORT11 - 0)
1693 #endif /* configBSP430_HPL_PORT11 */
1694 
1695 #if (configBSP430_HAL_PORT11 - 0) && ! (configBSP430_HPL_PORT11 - 0)
1696 #warning configBSP430_HAL_PORT11 requested without configBSP430_HPL_PORT11
1697 #endif /* HAL and not HPL */
1698 
1705 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT11 - 0)
1706 #define BSP430_PERIPH_PORT11 ((tBSP430periphHandle)(BSP430_PERIPH_PORT11_BASEADDRESS_))
1707 #endif /* configBSP430_HPL_PORT11 */
1708 
1709 /* END AUTOMATICALLY GENERATED CODE [periph_decl] */
1710 /* !BSP430! end=periph_decl */
1711 
1712 /* !BSP430! insert=port_hpl_decl */
1713 /* BEGIN AUTOMATICALLY GENERATED CODE---DO NOT MODIFY [port_hpl_decl] */
1728 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT1 - 0)
1729 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (1 <= 2)
1730 #define BSP430_HPL_PORT1 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT1)
1731 #else /* IE */
1732 #define BSP430_HPL_PORT1 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT1)
1733 #endif /* IE */
1734 #endif /* configBSP430_HPL_PORT1 */
1735 
1750 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT2 - 0)
1751 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (2 <= 2)
1752 #define BSP430_HPL_PORT2 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT2)
1753 #else /* IE */
1754 #define BSP430_HPL_PORT2 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT2)
1755 #endif /* IE */
1756 #endif /* configBSP430_HPL_PORT2 */
1757 
1772 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT3 - 0)
1773 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (3 <= 2)
1774 #define BSP430_HPL_PORT3 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT3)
1775 #else /* IE */
1776 #define BSP430_HPL_PORT3 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT3)
1777 #endif /* IE */
1778 #endif /* configBSP430_HPL_PORT3 */
1779 
1794 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT4 - 0)
1795 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (4 <= 2)
1796 #define BSP430_HPL_PORT4 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT4)
1797 #else /* IE */
1798 #define BSP430_HPL_PORT4 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT4)
1799 #endif /* IE */
1800 #endif /* configBSP430_HPL_PORT4 */
1801 
1816 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT5 - 0)
1817 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (5 <= 2)
1818 #define BSP430_HPL_PORT5 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT5)
1819 #else /* IE */
1820 #define BSP430_HPL_PORT5 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT5)
1821 #endif /* IE */
1822 #endif /* configBSP430_HPL_PORT5 */
1823 
1838 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT6 - 0)
1839 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (6 <= 2)
1840 #define BSP430_HPL_PORT6 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT6)
1841 #else /* IE */
1842 #define BSP430_HPL_PORT6 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT6)
1843 #endif /* IE */
1844 #endif /* configBSP430_HPL_PORT6 */
1845 
1860 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT7 - 0)
1861 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (7 <= 2)
1862 #define BSP430_HPL_PORT7 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT7)
1863 #else /* IE */
1864 #define BSP430_HPL_PORT7 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT7)
1865 #endif /* IE */
1866 #endif /* configBSP430_HPL_PORT7 */
1867 
1882 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT8 - 0)
1883 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (8 <= 2)
1884 #define BSP430_HPL_PORT8 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT8)
1885 #else /* IE */
1886 #define BSP430_HPL_PORT8 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT8)
1887 #endif /* IE */
1888 #endif /* configBSP430_HPL_PORT8 */
1889 
1904 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT9 - 0)
1905 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (9 <= 2)
1906 #define BSP430_HPL_PORT9 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT9)
1907 #else /* IE */
1908 #define BSP430_HPL_PORT9 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT9)
1909 #endif /* IE */
1910 #endif /* configBSP430_HPL_PORT9 */
1911 
1926 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT10 - 0)
1927 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (10 <= 2)
1928 #define BSP430_HPL_PORT10 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT10)
1929 #else /* IE */
1930 #define BSP430_HPL_PORT10 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT10)
1931 #endif /* IE */
1932 #endif /* configBSP430_HPL_PORT10 */
1933 
1948 #if defined(BSP430_DOXYGEN) || (configBSP430_HPL_PORT11 - 0)
1949 #if (BSP430_CORE_FAMILY_IS_5XX - 0) || (11 <= 2)
1950 #define BSP430_HPL_PORT11 ((volatile sBSP430hplPORTIE *)BSP430_PERIPH_PORT11)
1951 #else /* IE */
1952 #define BSP430_HPL_PORT11 ((volatile sBSP430hplPORT *)BSP430_PERIPH_PORT11)
1953 #endif /* IE */
1954 #endif /* configBSP430_HPL_PORT11 */
1955 
1956 /* END AUTOMATICALLY GENERATED CODE [port_hpl_decl] */
1957 /* !BSP430! end=port_hpl_decl */
1958 
1959 /* !BSP430! insert=hal_port_isr_decl */
1960 /* BEGIN AUTOMATICALLY GENERATED CODE---DO NOT MODIFY [hal_port_isr_decl] */
1976 #ifndef configBSP430_HAL_PORT1_ISR
1977 #define configBSP430_HAL_PORT1_ISR ((configBSP430_HAL_PORT1 - 0) && defined(PORT1_VECTOR))
1978 #endif /* configBSP430_HAL_PORT1_ISR */
1979 
1980 #if (configBSP430_HAL_PORT1_ISR - 0) && ! (configBSP430_HAL_PORT1 - 0)
1981 #warning configBSP430_HAL_PORT1_ISR requested without configBSP430_HAL_PORT1
1982 #endif /* HAL_ISR and not HAL */
1983 
1999 #ifndef configBSP430_HAL_PORT2_ISR
2000 #define configBSP430_HAL_PORT2_ISR ((configBSP430_HAL_PORT2 - 0) && defined(PORT2_VECTOR))
2001 #endif /* configBSP430_HAL_PORT2_ISR */
2002 
2003 #if (configBSP430_HAL_PORT2_ISR - 0) && ! (configBSP430_HAL_PORT2 - 0)
2004 #warning configBSP430_HAL_PORT2_ISR requested without configBSP430_HAL_PORT2
2005 #endif /* HAL_ISR and not HAL */
2006 
2022 #ifndef configBSP430_HAL_PORT3_ISR
2023 #define configBSP430_HAL_PORT3_ISR ((configBSP430_HAL_PORT3 - 0) && defined(PORT3_VECTOR))
2024 #endif /* configBSP430_HAL_PORT3_ISR */
2025 
2026 #if (configBSP430_HAL_PORT3_ISR - 0) && ! (configBSP430_HAL_PORT3 - 0)
2027 #warning configBSP430_HAL_PORT3_ISR requested without configBSP430_HAL_PORT3
2028 #endif /* HAL_ISR and not HAL */
2029 
2045 #ifndef configBSP430_HAL_PORT4_ISR
2046 #define configBSP430_HAL_PORT4_ISR ((configBSP430_HAL_PORT4 - 0) && defined(PORT4_VECTOR))
2047 #endif /* configBSP430_HAL_PORT4_ISR */
2048 
2049 #if (configBSP430_HAL_PORT4_ISR - 0) && ! (configBSP430_HAL_PORT4 - 0)
2050 #warning configBSP430_HAL_PORT4_ISR requested without configBSP430_HAL_PORT4
2051 #endif /* HAL_ISR and not HAL */
2052 
2068 #ifndef configBSP430_HAL_PORT5_ISR
2069 #define configBSP430_HAL_PORT5_ISR ((configBSP430_HAL_PORT5 - 0) && defined(PORT5_VECTOR))
2070 #endif /* configBSP430_HAL_PORT5_ISR */
2071 
2072 #if (configBSP430_HAL_PORT5_ISR - 0) && ! (configBSP430_HAL_PORT5 - 0)
2073 #warning configBSP430_HAL_PORT5_ISR requested without configBSP430_HAL_PORT5
2074 #endif /* HAL_ISR and not HAL */
2075 
2091 #ifndef configBSP430_HAL_PORT6_ISR
2092 #define configBSP430_HAL_PORT6_ISR ((configBSP430_HAL_PORT6 - 0) && defined(PORT6_VECTOR))
2093 #endif /* configBSP430_HAL_PORT6_ISR */
2094 
2095 #if (configBSP430_HAL_PORT6_ISR - 0) && ! (configBSP430_HAL_PORT6 - 0)
2096 #warning configBSP430_HAL_PORT6_ISR requested without configBSP430_HAL_PORT6
2097 #endif /* HAL_ISR and not HAL */
2098 
2114 #ifndef configBSP430_HAL_PORT7_ISR
2115 #define configBSP430_HAL_PORT7_ISR ((configBSP430_HAL_PORT7 - 0) && defined(PORT7_VECTOR))
2116 #endif /* configBSP430_HAL_PORT7_ISR */
2117 
2118 #if (configBSP430_HAL_PORT7_ISR - 0) && ! (configBSP430_HAL_PORT7 - 0)
2119 #warning configBSP430_HAL_PORT7_ISR requested without configBSP430_HAL_PORT7
2120 #endif /* HAL_ISR and not HAL */
2121 
2137 #ifndef configBSP430_HAL_PORT8_ISR
2138 #define configBSP430_HAL_PORT8_ISR ((configBSP430_HAL_PORT8 - 0) && defined(PORT8_VECTOR))
2139 #endif /* configBSP430_HAL_PORT8_ISR */
2140 
2141 #if (configBSP430_HAL_PORT8_ISR - 0) && ! (configBSP430_HAL_PORT8 - 0)
2142 #warning configBSP430_HAL_PORT8_ISR requested without configBSP430_HAL_PORT8
2143 #endif /* HAL_ISR and not HAL */
2144 
2160 #ifndef configBSP430_HAL_PORT9_ISR
2161 #define configBSP430_HAL_PORT9_ISR ((configBSP430_HAL_PORT9 - 0) && defined(PORT9_VECTOR))
2162 #endif /* configBSP430_HAL_PORT9_ISR */
2163 
2164 #if (configBSP430_HAL_PORT9_ISR - 0) && ! (configBSP430_HAL_PORT9 - 0)
2165 #warning configBSP430_HAL_PORT9_ISR requested without configBSP430_HAL_PORT9
2166 #endif /* HAL_ISR and not HAL */
2167 
2183 #ifndef configBSP430_HAL_PORT10_ISR
2184 #define configBSP430_HAL_PORT10_ISR ((configBSP430_HAL_PORT10 - 0) && defined(PORT10_VECTOR))
2185 #endif /* configBSP430_HAL_PORT10_ISR */
2186 
2187 #if (configBSP430_HAL_PORT10_ISR - 0) && ! (configBSP430_HAL_PORT10 - 0)
2188 #warning configBSP430_HAL_PORT10_ISR requested without configBSP430_HAL_PORT10
2189 #endif /* HAL_ISR and not HAL */
2190 
2206 #ifndef configBSP430_HAL_PORT11_ISR
2207 #define configBSP430_HAL_PORT11_ISR ((configBSP430_HAL_PORT11 - 0) && defined(PORT11_VECTOR))
2208 #endif /* configBSP430_HAL_PORT11_ISR */
2209 
2210 #if (configBSP430_HAL_PORT11_ISR - 0) && ! (configBSP430_HAL_PORT11 - 0)
2211 #warning configBSP430_HAL_PORT11_ISR requested without configBSP430_HAL_PORT11
2212 #endif /* HAL_ISR and not HAL */
2213 
2214 /* END AUTOMATICALLY GENERATED CODE [hal_port_isr_decl] */
2215 /* !BSP430! end=hal_port_isr_decl */
2216 
2229 static BSP430_CORE_INLINE
2230 volatile sBSP430hplPORTIE *
2232 {
2233  /* !BSP430! ie_test=<= subst=ie_test insert=periph_hpl_port_demux */
2234  /* BEGIN AUTOMATICALLY GENERATED CODE---DO NOT MODIFY [periph_hpl_port_demux] */
2235 #if (configBSP430_HPL_PORT1 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (1 <= 2))
2236  if (BSP430_PERIPH_PORT1 == periph) {
2237  return BSP430_HPL_PORT1;
2238  }
2239 #endif /* configBSP430_HPL_PORT1 */
2240 
2241 #if (configBSP430_HPL_PORT2 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (2 <= 2))
2242  if (BSP430_PERIPH_PORT2 == periph) {
2243  return BSP430_HPL_PORT2;
2244  }
2245 #endif /* configBSP430_HPL_PORT2 */
2246 
2247 #if (configBSP430_HPL_PORT3 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (3 <= 2))
2248  if (BSP430_PERIPH_PORT3 == periph) {
2249  return BSP430_HPL_PORT3;
2250  }
2251 #endif /* configBSP430_HPL_PORT3 */
2252 
2253 #if (configBSP430_HPL_PORT4 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (4 <= 2))
2254  if (BSP430_PERIPH_PORT4 == periph) {
2255  return BSP430_HPL_PORT4;
2256  }
2257 #endif /* configBSP430_HPL_PORT4 */
2258 
2259 #if (configBSP430_HPL_PORT5 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (5 <= 2))
2260  if (BSP430_PERIPH_PORT5 == periph) {
2261  return BSP430_HPL_PORT5;
2262  }
2263 #endif /* configBSP430_HPL_PORT5 */
2264 
2265 #if (configBSP430_HPL_PORT6 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (6 <= 2))
2266  if (BSP430_PERIPH_PORT6 == periph) {
2267  return BSP430_HPL_PORT6;
2268  }
2269 #endif /* configBSP430_HPL_PORT6 */
2270 
2271 #if (configBSP430_HPL_PORT7 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (7 <= 2))
2272  if (BSP430_PERIPH_PORT7 == periph) {
2273  return BSP430_HPL_PORT7;
2274  }
2275 #endif /* configBSP430_HPL_PORT7 */
2276 
2277 #if (configBSP430_HPL_PORT8 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (8 <= 2))
2278  if (BSP430_PERIPH_PORT8 == periph) {
2279  return BSP430_HPL_PORT8;
2280  }
2281 #endif /* configBSP430_HPL_PORT8 */
2282 
2283 #if (configBSP430_HPL_PORT9 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (9 <= 2))
2284  if (BSP430_PERIPH_PORT9 == periph) {
2285  return BSP430_HPL_PORT9;
2286  }
2287 #endif /* configBSP430_HPL_PORT9 */
2288 
2289 #if (configBSP430_HPL_PORT10 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (10 <= 2))
2290  if (BSP430_PERIPH_PORT10 == periph) {
2291  return BSP430_HPL_PORT10;
2292  }
2293 #endif /* configBSP430_HPL_PORT10 */
2294 
2295 #if (configBSP430_HPL_PORT11 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (11 <= 2))
2296  if (BSP430_PERIPH_PORT11 == periph) {
2297  return BSP430_HPL_PORT11;
2298  }
2299 #endif /* configBSP430_HPL_PORT11 */
2300 
2301  /* END AUTOMATICALLY GENERATED CODE [periph_hpl_port_demux] */
2302  /* !BSP430! end=periph_hpl_port_demux */
2303  return NULL;
2304 }
2305 
2316 static BSP430_CORE_INLINE
2317 volatile sBSP430hplPORT *
2319 {
2320  /* !BSP430! ie_test=> subst=ie_test insert=periph_hpl_port_demux */
2321  /* BEGIN AUTOMATICALLY GENERATED CODE---DO NOT MODIFY [periph_hpl_port_demux] */
2322 #if (configBSP430_HPL_PORT1 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (1 > 2))
2323  if (BSP430_PERIPH_PORT1 == periph) {
2324  return BSP430_HPL_PORT1;
2325  }
2326 #endif /* configBSP430_HPL_PORT1 */
2327 
2328 #if (configBSP430_HPL_PORT2 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (2 > 2))
2329  if (BSP430_PERIPH_PORT2 == periph) {
2330  return BSP430_HPL_PORT2;
2331  }
2332 #endif /* configBSP430_HPL_PORT2 */
2333 
2334 #if (configBSP430_HPL_PORT3 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (3 > 2))
2335  if (BSP430_PERIPH_PORT3 == periph) {
2336  return BSP430_HPL_PORT3;
2337  }
2338 #endif /* configBSP430_HPL_PORT3 */
2339 
2340 #if (configBSP430_HPL_PORT4 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (4 > 2))
2341  if (BSP430_PERIPH_PORT4 == periph) {
2342  return BSP430_HPL_PORT4;
2343  }
2344 #endif /* configBSP430_HPL_PORT4 */
2345 
2346 #if (configBSP430_HPL_PORT5 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (5 > 2))
2347  if (BSP430_PERIPH_PORT5 == periph) {
2348  return BSP430_HPL_PORT5;
2349  }
2350 #endif /* configBSP430_HPL_PORT5 */
2351 
2352 #if (configBSP430_HPL_PORT6 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (6 > 2))
2353  if (BSP430_PERIPH_PORT6 == periph) {
2354  return BSP430_HPL_PORT6;
2355  }
2356 #endif /* configBSP430_HPL_PORT6 */
2357 
2358 #if (configBSP430_HPL_PORT7 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (7 > 2))
2359  if (BSP430_PERIPH_PORT7 == periph) {
2360  return BSP430_HPL_PORT7;
2361  }
2362 #endif /* configBSP430_HPL_PORT7 */
2363 
2364 #if (configBSP430_HPL_PORT8 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (8 > 2))
2365  if (BSP430_PERIPH_PORT8 == periph) {
2366  return BSP430_HPL_PORT8;
2367  }
2368 #endif /* configBSP430_HPL_PORT8 */
2369 
2370 #if (configBSP430_HPL_PORT9 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (9 > 2))
2371  if (BSP430_PERIPH_PORT9 == periph) {
2372  return BSP430_HPL_PORT9;
2373  }
2374 #endif /* configBSP430_HPL_PORT9 */
2375 
2376 #if (configBSP430_HPL_PORT10 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (10 > 2))
2377  if (BSP430_PERIPH_PORT10 == periph) {
2378  return BSP430_HPL_PORT10;
2379  }
2380 #endif /* configBSP430_HPL_PORT10 */
2381 
2382 #if (configBSP430_HPL_PORT11 - 0) && ((BSP430_CORE_FAMILY_IS_5XX - 0) || (11 > 2))
2383  if (BSP430_PERIPH_PORT11 == periph) {
2384  return BSP430_HPL_PORT11;
2385  }
2386 #endif /* configBSP430_HPL_PORT11 */
2387 
2388  /* END AUTOMATICALLY GENERATED CODE [periph_hpl_port_demux] */
2389  /* !BSP430! end=periph_hpl_port_demux */
2390  return NULL;
2391 }
2392 
2401 static BSP430_CORE_INLINE
2402 hBSP430halPORT
2404 {
2405  /* !BSP430! insert=periph_hal_demux */
2406  /* BEGIN AUTOMATICALLY GENERATED CODE---DO NOT MODIFY [periph_hal_demux] */
2407 #if (configBSP430_HAL_PORT1 - 0)
2408  if (BSP430_PERIPH_PORT1 == periph) {
2409  return BSP430_HAL_PORT1;
2410  }
2411 #endif /* configBSP430_HAL_PORT1 */
2412 
2413 #if (configBSP430_HAL_PORT2 - 0)
2414  if (BSP430_PERIPH_PORT2 == periph) {
2415  return BSP430_HAL_PORT2;
2416  }
2417 #endif /* configBSP430_HAL_PORT2 */
2418 
2419 #if (configBSP430_HAL_PORT3 - 0)
2420  if (BSP430_PERIPH_PORT3 == periph) {
2421  return BSP430_HAL_PORT3;
2422  }
2423 #endif /* configBSP430_HAL_PORT3 */
2424 
2425 #if (configBSP430_HAL_PORT4 - 0)
2426  if (BSP430_PERIPH_PORT4 == periph) {
2427  return BSP430_HAL_PORT4;
2428  }
2429 #endif /* configBSP430_HAL_PORT4 */
2430 
2431 #if (configBSP430_HAL_PORT5 - 0)
2432  if (BSP430_PERIPH_PORT5 == periph) {
2433  return BSP430_HAL_PORT5;
2434  }
2435 #endif /* configBSP430_HAL_PORT5 */
2436 
2437 #if (configBSP430_HAL_PORT6 - 0)
2438  if (BSP430_PERIPH_PORT6 == periph) {
2439  return BSP430_HAL_PORT6;
2440  }
2441 #endif /* configBSP430_HAL_PORT6 */
2442 
2443 #if (configBSP430_HAL_PORT7 - 0)
2444  if (BSP430_PERIPH_PORT7 == periph) {
2445  return BSP430_HAL_PORT7;
2446  }
2447 #endif /* configBSP430_HAL_PORT7 */
2448 
2449 #if (configBSP430_HAL_PORT8 - 0)
2450  if (BSP430_PERIPH_PORT8 == periph) {
2451  return BSP430_HAL_PORT8;
2452  }
2453 #endif /* configBSP430_HAL_PORT8 */
2454 
2455 #if (configBSP430_HAL_PORT9 - 0)
2456  if (BSP430_PERIPH_PORT9 == periph) {
2457  return BSP430_HAL_PORT9;
2458  }
2459 #endif /* configBSP430_HAL_PORT9 */
2460 
2461 #if (configBSP430_HAL_PORT10 - 0)
2462  if (BSP430_PERIPH_PORT10 == periph) {
2463  return BSP430_HAL_PORT10;
2464  }
2465 #endif /* configBSP430_HAL_PORT10 */
2466 
2467 #if (configBSP430_HAL_PORT11 - 0)
2468  if (BSP430_PERIPH_PORT11 == periph) {
2469  return BSP430_HAL_PORT11;
2470  }
2471 #endif /* configBSP430_HAL_PORT11 */
2472 
2473  /* END AUTOMATICALLY GENERATED CODE [periph_hal_demux] */
2474  /* !BSP430! end=periph_hal_demux */
2475  return NULL;
2476 }
2477 
2484 const char * xBSP430portName (tBSP430periphHandle periph);
2485 
2499 static BSP430_CORE_INLINE
2500 int
2501 iBSP430portBitPosition (unsigned int bitx)
2502 {
2503  unsigned char bit = 0x01;
2504  int rv = 0;
2505  while (bit && !(bit & bitx)) {
2506  bit <<= 1;
2507  ++rv;
2508  }
2509  return bit ? rv : -1;
2510 }
2511 
2512 #endif /* BSP430_MODULE_PORT */
2513 
2514 #endif /* BSP430_PERIPH_PORT_H */
unsigned char sel
Definition: port.h:598
uBSP430hplPORT_16 ie
Definition: port.h:576
#define BSP430_HAL_PORT8
Definition: port.h:1227
unsigned char sel1
Definition: port.h:602
#define BSP430_PERIPH_PORT7
Definition: port.h:1574
sBSP430hplPORT_8 sBSP430hplPORT
Definition: port.h:636
#define BSP430_PERIPH_PORT11
Definition: port.h:1706
#define BSP430_HAL_PORT11
Definition: port.h:1338
unsigned char h
Definition: port.h:542
unsigned char dir
Definition: port.h:590
sBSP430hplHALStatePrefix hal_state
Definition: port.h:841
volatile sBSP430hplPORT_5XX_16 * port_5xx_16
Definition: port.h:861
unsigned char in
Definition: port.h:586
struct sBSP430halPORT sBSP430halPORT
unsigned char ie
Definition: port.h:616
Definition: port.h:559
volatile sBSP430hplPORTIE * portie
Definition: port.h:863
uBSP430hplPORT_16 ren
Definition: port.h:563
#define BSP430_HPL_PORT8
Definition: port.h:1886
struct sBSP430hplPORT_5XX_8 sBSP430hplPORT_5XX_8
Definition: port.h:550
static BSP430_CORE_INLINE volatile sBSP430hplPORTIE * xBSP430hplLookupPORTIE(tBSP430periphHandle periph)
Definition: port.h:2231
#define BSP430_HAL_PORT4
Definition: port.h:1079
#define BSP430_HPL_PORT1
Definition: port.h:1730
unsigned char ren
Definition: port.h:592
const struct sBSP430halISRIndexedChainNode *volatile pin_cbchain_ni[8]
Definition: port.h:871
#define BSP430_PERIPH_PORT8
Definition: port.h:1607
volatile sBSP430hplPORT_IE_8 * port_ie_8
Definition: port.h:853
Definition: port.h:537
static BSP430_CORE_INLINE hBSP430halPORT hBSP430portLookup(tBSP430periphHandle periph)
Definition: port.h:2403
#define BSP430_PERIPH_PORT5
Definition: port.h:1508
struct sBSP430halPORT * hBSP430halPORT
Definition: port.h:895
const char * xBSP430portName(tBSP430periphHandle periph)
#define BSP430_PERIPH_PORT3
Definition: port.h:1442
#define BSP430_HPL_PORT3
Definition: port.h:1776
volatile unsigned char *const sel2p
Definition: port.h:890
uBSP430hplPORT_16 in
Definition: port.h:560
#define BSP430_PERIPH_PORT9
Definition: port.h:1640
#define BSP430_HPL_PORT6
Definition: port.h:1842
#define BSP430_HAL_PORT7
Definition: port.h:1190
unsigned char ifg
Definition: port.h:618
#define BSP430_HPL_PORT9
Definition: port.h:1908
uBSP430hplPORT_16 out
Definition: port.h:561
sBSP430hplPORT_16 sBSP430hplPORTW
Definition: port.h:645
#define BSP430_HPL_PORT10
Definition: port.h:1930
#define BSP430_PERIPH_PORT4
Definition: port.h:1475
uBSP430hplPORT_16 selc
Definition: port.h:574
#define BSP430_CORE_INLINE
Definition: core.h:439
Generic peripheral support for MSP430 MCUs.
#define BSP430_HAL_PORT10
Definition: port.h:1301
volatile sBSP430hplPORT_8 * port_8
Definition: port.h:855
unsigned char b[2]
Definition: port.h:539
#define BSP430_PERIPH_PORT6
Definition: port.h:1541
unsigned char ds
Definition: port.h:594
uBSP430hplPORT_16 ifg
Definition: port.h:577
Definition: periph.h:437
volatile sBSP430hplPORTW * portw
Definition: port.h:867
unsigned char l
Definition: port.h:541
volatile void * any
Definition: port.h:851
#define BSP430_HAL_PORT6
Definition: port.h:1153
#define BSP430_HAL_PORT1
Definition: port.h:968
#define BSP430_HPL_PORT11
Definition: port.h:1952
Definition: port.h:838
#define BSP430_HAL_PORT2
Definition: port.h:1005
#define BSP430_PERIPH_PORT2
Definition: port.h:1409
struct sBSP430hplPORT_IE_8 sBSP430hplPORT_IE_8
#define BSP430_HPL_PORT5
Definition: port.h:1820
#define BSP430_PERIPH_PORT1
Definition: port.h:1376
uBSP430hplPORT_16 ies
Definition: port.h:575
Definition: port.h:585
union sBSP430halPORT::@30 hpl
volatile sBSP430hplPORT_5XX_8 * port_5xx_8
Definition: port.h:859
Definition: port.h:529
Definition: port.h:514
uBSP430hplPORT_16 ds
Definition: port.h:564
struct sBSP430hplPORT_16 sBSP430hplPORT_16
volatile unsigned char *const renp
Definition: port.h:880
unsigned char sel0
Definition: port.h:599
unsigned int w
Definition: port.h:538
static BSP430_CORE_INLINE int iBSP430portBitPosition(unsigned int bitx)
Definition: port.h:2501
sBSP430hplPORT_IE_8 sBSP430hplPORTIE
Definition: port.h:627
volatile sBSP430hplPORT * port
Definition: port.h:865
struct sBSP430hplPORT_5XX_16 sBSP430hplPORT_5XX_16
struct sBSP430hplPORT_8 sBSP430hplPORT_8
uBSP430hplPORT_16 sel
Definition: port.h:566
uBSP430hplPORT_16 sel1
Definition: port.h:569
#define BSP430_HAL_PORT9
Definition: port.h:1264
unsigned char out
Definition: port.h:588
uBSP430hplPORT_16 sel0
Definition: port.h:567
int tBSP430periphHandle
Definition: periph.h:106
#define BSP430_HPL_PORT4
Definition: port.h:1798
volatile sBSP430hplPORT_16 * port_16
Definition: port.h:857
uBSP430hplPORT_16 dir
Definition: port.h:562
static BSP430_CORE_INLINE volatile sBSP430hplPORT * xBSP430hplLookupPORT(tBSP430periphHandle periph)
Definition: port.h:2318
#define BSP430_PERIPH_PORT10
Definition: port.h:1673
unsigned char ies
Definition: port.h:614
Definition: periph.h:272
#define BSP430_HPL_PORT2
Definition: port.h:1752
#define BSP430_HAL_PORT3
Definition: port.h:1042
union uBSP430hplPORT_16 uBSP430hplPORT_16
unsigned char selc
Definition: port.h:612
#define BSP430_HAL_PORT5
Definition: port.h:1116
#define BSP430_HPL_PORT7
Definition: port.h:1864