nrfcxx  0.1.0
C++-17 Framework for Nordic nRF5 Devices
core832.hpp
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1 /* SPDX-License-Identifier: Apache-2.0 */
2 /* Copyright 2018-2019 Peter A. Bigot */
3 
7 #ifndef NRFCXX_NRF52832_CORE_HPP
8 #define NRFCXX_NRF52832_CORE_HPP
9 #pragma once
10 
11 #include <nrf52.h>
12 
14 /* Forward declarations for IRQ handlers. */
15 extern "C" {
16 void POWER_CLOCK_IRQHandler ();
17 void RADIO_IRQHandler ();
18 void UARTE0_UART0_IRQHandler ();
19 void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler ();
20 void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler ();
21 void NFCT_IRQHandler ();
22 void GPIOTE_IRQHandler ();
23 void SAADC_IRQHandler ();
24 void TIMER0_IRQHandler ();
25 void TIMER1_IRQHandler ();
26 void TIMER2_IRQHandler ();
27 void RTC0_IRQHandler ();
28 void TEMP_IRQHandler ();
29 void RNG_IRQHandler ();
30 void ECB_IRQHandler ();
31 void CCM_AAR_IRQHandler ();
32 void WDT_IRQHandler ();
33 void RTC1_IRQHandler ();
34 void QDEC_IRQHandler ();
35 void COMP_LPCOMP_IRQHandler ();
36 void SWI0_EGU0_IRQHandler ();
37 void SWI1_EGU1_IRQHandler ();
38 void SWI2_EGU2_IRQHandler ();
39 void SWI3_EGU3_IRQHandler ();
40 void SWI4_EGU4_IRQHandler ();
41 void SWI5_EGU5_IRQHandler ();
42 void TIMER3_IRQHandler ();
43 void TIMER4_IRQHandler ();
44 void PWM0_IRQHandler ();
45 void PDM_IRQHandler ();
46 void MWU_IRQHandler ();
47 void PWM1_IRQHandler ();
48 void PWM2_IRQHandler ();
49 void SPIM2_SPIS2_SPI2_IRQHandler ();
50 void RTC2_IRQHandler ();
51 void I2S_IRQHandler ();
52 void FPU_IRQHandler ();
53 }
56 namespace nrfcxx {
57 namespace nrf5 {
58 
59 using FICR_Type = peripheral<NRF_FICR_Type>;
60 static constexpr FICR_Type FICR{NRF_FICR_BASE};
61 
62 using UICR_Type = peripheral<NRF_UICR_Type>;
63 static constexpr UICR_Type UICR{NRF_UICR_BASE};
64 
65 using BPROT_Type = peripheral<NRF_BPROT_Type>;
66 static constexpr BPROT_Type BPROT{NRF_BPROT_BASE};
67 
68 using POWER_Type = peripheral<NRF_POWER_Type>;
69 static constexpr POWER_Type POWER{NRF_POWER_BASE, POWER_CLOCK_IRQn};
70 
71 using CLOCK_Type = peripheral<NRF_CLOCK_Type>;
72 static constexpr CLOCK_Type CLOCK{NRF_CLOCK_BASE, POWER_CLOCK_IRQn};
73 
74 using RADIO_Type = peripheral<NRF_RADIO_Type>;
75 static constexpr RADIO_Type RADIO{NRF_RADIO_BASE, RADIO_IRQn};
76 
77 using UARTE_Type = peripheral<NRF_UARTE_Type>;
78 static constexpr UARTE_Type UARTE0{NRF_UARTE0_BASE, UARTE0_UART0_IRQn};
79 
80 using UART_Type = peripheral<NRF_UART_Type>;
81 static constexpr UART_Type UART0{NRF_UART0_BASE, UARTE0_UART0_IRQn};
82 
83 using SPIM_Type = peripheral<NRF_SPIM_Type>;
84 static constexpr SPIM_Type SPIM0{NRF_SPIM0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
85 static constexpr SPIM_Type SPIM1{NRF_SPIM1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
86 static constexpr SPIM_Type SPIM2{NRF_SPIM2_BASE, SPIM2_SPIS2_SPI2_IRQn, 2};
87 
88 using SPIS_Type = peripheral<NRF_SPIS_Type>;
89 static constexpr SPIS_Type SPIS0{NRF_SPIS0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
90 static constexpr SPIS_Type SPIS1{NRF_SPIS1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
91 static constexpr SPIS_Type SPIS2{NRF_SPIS2_BASE, SPIM2_SPIS2_SPI2_IRQn, 2};
92 
93 using SPI_Type = peripheral<NRF_SPI_Type>;
94 static constexpr SPI_Type SPI0{NRF_SPI0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
95 static constexpr SPI_Type SPI1{NRF_SPI1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
96 static constexpr SPI_Type SPI2{NRF_SPI2_BASE, SPIM2_SPIS2_SPI2_IRQn, 2};
97 
98 using TWIM_Type = peripheral<NRF_TWIM_Type>;
99 static constexpr TWIM_Type TWIM0{NRF_TWIM0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
100 static constexpr TWIM_Type TWIM1{NRF_TWIM1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
101 
102 using TWIS_Type = peripheral<NRF_TWIS_Type>;
103 static constexpr TWIS_Type TWIS0{NRF_TWIS0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
104 static constexpr TWIS_Type TWIS1{NRF_TWIS1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
105 
106 using TWI_Type = peripheral<NRF_TWI_Type>;
107 static constexpr TWI_Type TWI0{NRF_TWI0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
108 static constexpr TWI_Type TWI1{NRF_TWI1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
109 
110 using NFCT_Type = peripheral<NRF_NFCT_Type>;
111 static constexpr NFCT_Type NFCT{NRF_NFCT_BASE, NFCT_IRQn};
112 
113 using GPIOTE_Type = peripheral<NRF_GPIOTE_Type>;
114 static constexpr GPIOTE_Type GPIOTE{NRF_GPIOTE_BASE, GPIOTE_IRQn, GPIOTE_Type::NO_INSTANCE, 8};
115 
116 using SAADC_Type = peripheral<NRF_SAADC_Type>;
117 static constexpr SAADC_Type SAADC{NRF_SAADC_BASE, SAADC_IRQn, SAADC_Type::NO_INSTANCE, 8};
118 static constexpr auto& ADCVariant = SAADC;
119 #define ADCSeriesVariant_IRQHandler SAADC_IRQHandler
120 
121 using TIMER_Type = peripheral<NRF_TIMER_Type>;
122 static constexpr TIMER_Type TIMER0{NRF_TIMER0_BASE, TIMER0_IRQn, 0, 4};
123 static constexpr TIMER_Type TIMER1{NRF_TIMER1_BASE, TIMER1_IRQn, 1, 4};
124 static constexpr TIMER_Type TIMER2{NRF_TIMER2_BASE, TIMER2_IRQn, 2, 4};
125 static constexpr TIMER_Type TIMER3{NRF_TIMER3_BASE, TIMER3_IRQn, 3, 6};
126 static constexpr TIMER_Type TIMER4{NRF_TIMER4_BASE, TIMER4_IRQn, 4, 6};
127 
128 using RTC_Type = peripheral<NRF_RTC_Type>;
129 static constexpr RTC_Type RTC0{NRF_RTC0_BASE, RTC0_IRQn, 0, 3};
130 static constexpr RTC_Type RTC1{NRF_RTC1_BASE, RTC1_IRQn, 1, 4};
131 static constexpr RTC_Type RTC2{NRF_RTC2_BASE, RTC2_IRQn, 2, 4};
132 #define UPTIME_RTC_IRQHandler RTC1_IRQHandler
133 static constexpr const RTC_Type& UPTIME_RTC{RTC1};
134 
135 using TEMP_Type = peripheral<NRF_TEMP_Type>;
136 static constexpr TEMP_Type TEMP{NRF_TEMP_BASE, TEMP_IRQn};
137 
138 using RNG_Type = peripheral<NRF_RNG_Type>;
139 static constexpr RNG_Type RNG{NRF_RNG_BASE, RNG_IRQn};
140 
141 using ECB_Type = peripheral<NRF_ECB_Type>;
142 static constexpr ECB_Type ECB{NRF_ECB_BASE, ECB_IRQn};
143 
144 using CCM_Type = peripheral<NRF_CCM_Type>;
145 static constexpr CCM_Type CCM{NRF_CCM_BASE, CCM_AAR_IRQn};
146 
147 using AAR_Type = peripheral<NRF_AAR_Type>;
148 static constexpr AAR_Type AAR{NRF_AAR_BASE, CCM_AAR_IRQn};
149 
150 using WDT_Type = peripheral<NRF_WDT_Type>;
151 static constexpr WDT_Type WDT{NRF_WDT_BASE, WDT_IRQn};
152 
153 using QDEC_Type = peripheral<NRF_QDEC_Type>;
154 static constexpr QDEC_Type QDEC{NRF_QDEC_BASE, QDEC_IRQn};
155 
156 using COMP_Type = peripheral<NRF_COMP_Type>;
157 static constexpr COMP_Type COMP{NRF_COMP_BASE, COMP_LPCOMP_IRQn};
158 
159 using LPCOMP_Type = peripheral<NRF_LPCOMP_Type>;
160 static constexpr LPCOMP_Type LPCOMP{NRF_LPCOMP_BASE, COMP_LPCOMP_IRQn};
161 
162 using SWI_Type = peripheral<NRF_SWI_Type>;
163 static constexpr SWI_Type SWI0{NRF_SWI0_BASE, SWI0_EGU0_IRQn, 0};
164 static constexpr SWI_Type SWI1{NRF_SWI1_BASE, SWI1_EGU1_IRQn, 1};
165 static constexpr SWI_Type SWI2{NRF_SWI2_BASE, SWI2_EGU2_IRQn, 2};
166 static constexpr SWI_Type SWI3{NRF_SWI3_BASE, SWI3_EGU3_IRQn, 3};
167 static constexpr SWI_Type SWI4{NRF_SWI4_BASE, SWI4_EGU4_IRQn, 4};
168 static constexpr SWI_Type SWI5{NRF_SWI5_BASE, SWI5_EGU5_IRQn, 5};
169 
170 using EGU_Type = peripheral<NRF_EGU_Type>;
171 static constexpr EGU_Type EGU0{NRF_EGU0_BASE, SWI0_EGU0_IRQn, 0};
172 static constexpr EGU_Type EGU1{NRF_EGU1_BASE, SWI1_EGU1_IRQn, 1};
173 static constexpr EGU_Type EGU2{NRF_EGU2_BASE, SWI2_EGU2_IRQn, 2};
174 static constexpr EGU_Type EGU3{NRF_EGU3_BASE, SWI3_EGU3_IRQn, 3};
175 static constexpr EGU_Type EGU4{NRF_EGU4_BASE, SWI4_EGU4_IRQn, 4};
176 static constexpr EGU_Type EGU5{NRF_EGU5_BASE, SWI5_EGU5_IRQn, 5};
177 
178 using PWM_Type = peripheral<NRF_PWM_Type>;
179 static constexpr PWM_Type PWM0{NRF_PWM0_BASE, PWM0_IRQn, 0};
180 static constexpr PWM_Type PWM1{NRF_PWM1_BASE, PWM1_IRQn, 1};
181 static constexpr PWM_Type PWM2{NRF_PWM2_BASE, PWM2_IRQn, 2};
182 
183 using PDM_Type = peripheral<NRF_PDM_Type>;
184 static constexpr PDM_Type PDM0{NRF_PDM_BASE, PDM_IRQn};
185 
186 using NVMC_Type = peripheral<NRF_NVMC_Type>;
187 static constexpr NVMC_Type NVMC{NRF_NVMC_BASE};
188 
189 struct PPI_Type : public peripheral<NRF_PPI_Type>
190 {
194  static constexpr size_t NUM_CHANNELS = 20;
195 
197  using channel_set_type = uint32_t;
198 
200  static constexpr size_t NUM_GROUPS = 4;
201 
203  using group_set_type = uint8_t;
204 
205  constexpr PPI_Type () :
206  peripheral<NRF_PPI_Type>{NRF_PPI_BASE, PPI_Type::NO_IRQ, PPI_Type::NO_INSTANCE, NUM_CHANNELS}
207  { }
208 };
209 static constexpr PPI_Type PPI{};
210 
211 using MWU_Type = peripheral<NRF_MWU_Type>;
212 static constexpr MWU_Type MWU{NRF_MWU_BASE, MWU_IRQn};
213 
214 using I2S_Type = peripheral<NRF_I2S_Type>;
215 static constexpr I2S_Type I2S{NRF_I2S_BASE, I2S_IRQn};
216 
217 #if 0
218 /* Nordic defines their macro as FPU instead of NRF_FPU */
219 using FPU_Type = peripheral<NRF_FPU_Type>;
220 static constexpr FPU_Type FPU{NRF_FPU_BASE, FPU_IRQn};
221 #endif
222 
223 using GPIO_Type = peripheral<NRF_GPIO_Type>;
224 static constexpr GPIO_Type P0{NRF_P0_BASE, GPIO_Type::NO_IRQ, 0, 32};
225 static constexpr int GPIO_PSEL_COUNT = 32;
226 static constexpr const GPIO_Type& GPIO{P0};
227 
228 template <>
229 struct GPIO_Instance<0>
230 {
231  static constexpr const GPIO_Type& peripheral{P0};
232  static constexpr int begin_psel = 0;
233  static constexpr int end_psel = begin_psel + P0.AUX;
234 };
235 
236 } // ns nrf5
237 } // ns nrfcxx
238 
239 #endif /* NRFCXX_NRF52832_HPP */
nrfcxx::nrf5::PPI_Type
Definition: core.hpp:147
nrfcxx::nrf5::peripheral< NRF_PPI_Type >::NO_IRQ
static constexpr int8_t NO_IRQ
Flag value for IRQn indicating that the peripheral does not have an assign interrupt vector entry.
Definition: core.hpp:172
nrfcxx::nrf5::GPIO_PSEL_COUNT
static constexpr int GPIO_PSEL_COUNT
The number of GPIO PSEL ordinals supported by the platform.
Definition: core.hpp:178
nrfcxx::nrf5::peripheral
Capture information about an nRF5 peripheral instance.
Definition: core.hpp:165
nrfcxx::nrf5::peripheral::AUX
const uint8_t AUX
Auxiliary information relevant to the specific peripheral and type.
Definition: core.hpp:245
nrfcxx::nrf5::PPI_Type::NUM_GROUPS
static constexpr size_t NUM_GROUPS
The number of channel groups.
Definition: core.hpp:157
nrfcxx::nrf5::PPI_Type::NUM_CHANNELS
static constexpr size_t NUM_CHANNELS
The number of configurable channels.
Definition: core.hpp:151
nrfcxx::nrf5::PPI_Type::group_set_type
uint8_t group_set_type
Bit-mask type to record sets of configurable channels.
Definition: core.hpp:160
nrfcxx::nrf5::peripheral::NO_INSTANCE
static constexpr uint8_t NO_INSTANCE
Flag value for INSTANCE indicating that the peripheral does not have enumerated instances (e....
Definition: core.hpp:177
nrfcxx::nrf5::PPI_Type::channel_set_type
uint16_t channel_set_type
Bit-mask type to record sets of configurable channels.
Definition: core.hpp:154
nrfcxx
Primary namespace for nrfcxx functionality.
Definition: clock.hpp:17
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