nrfcxx  0.1.0
C++-17 Framework for Nordic nRF5 Devices
core.hpp
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1 /* SPDX-License-Identifier: Apache-2.0 */
2 /* Copyright 2015-2019 Peter A. Bigot */
3 
8 #ifndef NRFCXX_NRF51_CORE_HPP
9 #define NRFCXX_NRF51_CORE_HPP
10 #pragma once
11 
12 #include <nrf51.h>
13 
15 /* Forward declarations for IRQ handlers. */
16 extern "C" {
17 void POWER_CLOCK_IRQHandler ();
18 void RADIO_IRQHandler ();
19 void UART0_IRQHandler ();
20 void SPI0_TWI0_IRQHandler ();
21 void SPI1_TWI1_IRQHandler ();
22 void GPIOTE_IRQHandler ();
23 void ADC_IRQHandler ();
24 void TIMER0_IRQHandler ();
25 void TIMER1_IRQHandler ();
26 void TIMER2_IRQHandler ();
27 void RTC0_IRQHandler ();
28 void TEMP_IRQHandler ();
29 void RNG_IRQHandler ();
30 void ECB_IRQHandler ();
31 void CCM_AAR_IRQHandler ();
32 void WDT_IRQHandler ();
33 void RTC1_IRQHandler ();
34 void QDEC_IRQHandler ();
35 void LPCOMP_IRQHandler ();
36 void SWI0_IRQHandler ();
37 void SWI1_IRQHandler ();
38 void SWI2_IRQHandler ();
39 void SWI3_IRQHandler ();
40 void SWI4_IRQHandler ();
41 void SWI5_IRQHandler ();
42 }
45 namespace nrfcxx {
46 namespace nrf5 {
47 namespace series {
48 
50 static constexpr unsigned int CLOCK_MHz = 16;
51 
65 static constexpr unsigned int DELAY_US_OVERHEAD_cyc = 11;
66 
68 void delay_cycles (unsigned int cycles);
69 
70 } // ns series
71 
72 using POWER_Type = nrf5::peripheral<NRF_POWER_Type>;
73 static constexpr POWER_Type POWER{NRF_POWER_BASE, POWER_CLOCK_IRQn};
74 
75 using CLOCK_Type = peripheral<NRF_CLOCK_Type>;
76 static constexpr CLOCK_Type CLOCK{NRF_CLOCK_BASE, POWER_CLOCK_IRQn};
77 
78 using MPU_Type = peripheral<NRF_MPU_Type>;
79 static constexpr MPU_Type MPU{NRF_MPU_BASE};
80 
81 using RADIO_Type = peripheral<NRF_RADIO_Type>;
82 static constexpr RADIO_Type RADIO{NRF_RADIO_BASE, RADIO_IRQn};
83 
84 using UART_Type = peripheral<NRF_UART_Type>;
85 static constexpr UART_Type UART0{NRF_UART0_BASE, UART0_IRQn, 0};
86 
87 using SPI_Type = peripheral<NRF_SPI_Type>;
88 static constexpr SPI_Type SPI0{NRF_SPI0_BASE, SPI0_TWI0_IRQn, 0};
89 static constexpr SPI_Type SPI1{NRF_SPI1_BASE, SPI1_TWI1_IRQn, 1};
90 
91 using TWI_Type = peripheral<NRF_TWI_Type>;
92 static constexpr TWI_Type TWI0{NRF_TWI0_BASE, SPI0_TWI0_IRQn, 0};
93 static constexpr TWI_Type TWI1{NRF_TWI1_BASE, SPI1_TWI1_IRQn, 1};
94 
95 using SPIS_Type = peripheral<NRF_SPIS_Type>;
96 static constexpr SPI_Type SPIS1{NRF_SPIS1_BASE, SPI1_TWI1_IRQn, 1};
97 
98 using GPIOTE_Type = peripheral<NRF_GPIOTE_Type>;
99 static constexpr GPIOTE_Type GPIOTE{NRF_GPIOTE_BASE, GPIOTE_IRQn, GPIOTE_Type::NO_INSTANCE, 4};
100 
101 using ADC_Type = peripheral<NRF_ADC_Type>;
102 static constexpr ADC_Type ADC{NRF_ADC_BASE, ADC_IRQn};
103 static constexpr auto& ADCVariant = ADC;
104 #define ADCSeriesVariant_IRQHandler ADC_IRQHandler
105 
106 using TIMER_Type = peripheral<NRF_TIMER_Type>;
107 static constexpr TIMER_Type TIMER0{NRF_TIMER0_BASE, TIMER0_IRQn, 0, 4};
108 static constexpr TIMER_Type TIMER1{NRF_TIMER1_BASE, TIMER1_IRQn, 1, 4};
109 static constexpr TIMER_Type TIMER2{NRF_TIMER2_BASE, TIMER2_IRQn, 2, 4};
110 
111 using RTC_Type = peripheral<NRF_RTC_Type>;
112 static constexpr RTC_Type RTC0{NRF_RTC0_BASE, RTC0_IRQn, 0, 3};
113 static constexpr RTC_Type RTC1{NRF_RTC1_BASE, RTC1_IRQn, 0, 4};
114 #define UPTIME_RTC_IRQHandler RTC1_IRQHandler
115 static constexpr const RTC_Type& UPTIME_RTC{RTC1};
116 
117 using TEMP_Type = peripheral<NRF_TEMP_Type>;
118 static constexpr TEMP_Type TEMP{NRF_TEMP_BASE, TEMP_IRQn};
119 
120 using RNG_Type = peripheral<NRF_RNG_Type>;
121 static constexpr RNG_Type RNG{NRF_RNG_BASE, RNG_IRQn};
122 
123 using ECB_Type = peripheral<NRF_ECB_Type>;
124 static constexpr ECB_Type ECB{NRF_ECB_BASE, ECB_IRQn};
125 
126 using AAR_Type = peripheral<NRF_AAR_Type>;
127 static constexpr AAR_Type AAR{NRF_AAR_BASE, CCM_AAR_IRQn};
128 
129 using CCM_Type = peripheral<NRF_CCM_Type>;
130 static constexpr CCM_Type CCM{NRF_CCM_BASE, CCM_AAR_IRQn};
131 
132 using WDT_Type = peripheral<NRF_WDT_Type>;
133 static constexpr WDT_Type WDT{NRF_WDT_BASE, WDT_IRQn};
134 
135 using QDEC_Type = peripheral<NRF_QDEC_Type>;
136 static constexpr QDEC_Type QDEC{NRF_QDEC_BASE, QDEC_IRQn};
137 
138 using LPCOMP_Type = peripheral<NRF_LPCOMP_Type>;
139 static constexpr LPCOMP_Type LPCOMP{NRF_LPCOMP_BASE, LPCOMP_IRQn};
140 
141 using SWI_Type = peripheral<NRF_SWI_Type>;
142 static constexpr SWI_Type SWI{NRF_SWI_BASE};
143 
144 using NVMC_Type = peripheral<NRF_NVMC_Type>;
145 static constexpr NVMC_Type NVMC{NRF_NVMC_BASE};
146 
147 struct PPI_Type : public peripheral<NRF_PPI_Type> {
151  static constexpr size_t NUM_CHANNELS = 16;
152 
154  using channel_set_type = uint16_t;
155 
157  static constexpr size_t NUM_GROUPS = 4;
158 
160  using group_set_type = uint8_t;
161 
162  constexpr PPI_Type () :
163  peripheral<NRF_PPI_Type>{NRF_PPI_BASE, PPI_Type::NO_IRQ, PPI_Type::NO_INSTANCE, NUM_CHANNELS}
164  { }
165 };
166 static constexpr PPI_Type PPI{};
167 
168 using FICR_Type = peripheral<NRF_FICR_Type>;
169 static constexpr FICR_Type FICR{NRF_FICR_BASE};
170 
171 using UICR_Type = peripheral<NRF_UICR_Type>;
172 static constexpr UICR_Type UICR{NRF_UICR_BASE};
173 
174 using GPIO_Type = peripheral<NRF_GPIO_Type>;
178 static constexpr int GPIO_PSEL_COUNT = 32;
179 static constexpr GPIO_Type GPIO{NRF_GPIO_BASE, GPIO_Type::NO_IRQ, 0, 32};
180 
181 template <>
182 struct GPIO_Instance<0> {
183  static constexpr const GPIO_Type& peripheral{GPIO};
184  static constexpr int begin_psel = 0;
185  static constexpr int end_psel = begin_psel + GPIO.AUX;
186 };
187 
188 } // ns nrf5
189 } // ns nrfcxx
190 
191 #endif /* NRFCXX_NRF51_CORE_HPP */
nrfcxx::nrf5::PPI_Type
Definition: core.hpp:147
nrfcxx::nrf5::peripheral< NRF_PPI_Type >::NO_IRQ
static constexpr int8_t NO_IRQ
Flag value for IRQn indicating that the peripheral does not have an assign interrupt vector entry.
Definition: core.hpp:172
nrfcxx::nrf5::GPIO_PSEL_COUNT
static constexpr int GPIO_PSEL_COUNT
The number of GPIO PSEL ordinals supported by the platform.
Definition: core.hpp:178
nrfcxx::nrf5::peripheral
Capture information about an nRF5 peripheral instance.
Definition: core.hpp:165
nrfcxx::nrf5::peripheral::AUX
const uint8_t AUX
Auxiliary information relevant to the specific peripheral and type.
Definition: core.hpp:245
nrfcxx::nrf5::series::DELAY_US_OVERHEAD_cyc
static constexpr unsigned int DELAY_US_OVERHEAD_cyc
Overhead setting up the call to delay_cycles() in the standard delay_us() implementation.
Definition: core.hpp:65
nrfcxx::nrf5::GPIO_Instance
A traits type identifying GPIO peripheral instances.
Definition: core.hpp:260
nrfcxx::nrf5::series::delay_cycles
void delay_cycles(unsigned int cycles)
Loop to delay for a requested number of cycles.
nrfcxx::nrf5::PPI_Type::NUM_GROUPS
static constexpr size_t NUM_GROUPS
The number of channel groups.
Definition: core.hpp:157
nrfcxx::nrf5::PPI_Type::NUM_CHANNELS
static constexpr size_t NUM_CHANNELS
The number of configurable channels.
Definition: core.hpp:151
nrfcxx::nrf5::PPI_Type::group_set_type
uint8_t group_set_type
Bit-mask type to record sets of configurable channels.
Definition: core.hpp:160
nrfcxx::nrf5::peripheral::NO_INSTANCE
static constexpr uint8_t NO_INSTANCE
Flag value for INSTANCE indicating that the peripheral does not have enumerated instances (e....
Definition: core.hpp:177
nrfcxx::nrf5::series::CLOCK_MHz
static constexpr unsigned int CLOCK_MHz
CPU clock speed in MHz.
Definition: core.hpp:50
nrfcxx::nrf5::PPI_Type::channel_set_type
uint16_t channel_set_type
Bit-mask type to record sets of configurable channels.
Definition: core.hpp:154
nrfcxx
Primary namespace for nrfcxx functionality.
Definition: clock.hpp:17
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