nrfcxx  0.1.0
C++-17 Framework for Nordic nRF5 Devices
core840.hpp
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1 /* SPDX-License-Identifier: Apache-2.0 */
2 /* Copyright 2018-2019 Peter A. Bigot */
3 
8 #ifndef NRFCXX_NRF52840_CORE_HPP
9 #define NRFCXX_NRF52840_CORE_HPP
10 #pragma once
11 
12 #include <nrf52840.h>
13 
15 /* Forward declarations for IRQ handlers. */
16 extern "C" {
17 void POWER_CLOCK_IRQHandler ();
18 void RADIO_IRQHandler ();
19 void UARTE0_UART0_IRQHandler ();
20 void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler ();
21 void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler ();
22 void NFCT_IRQHandler ();
23 void GPIOTE_IRQHandler ();
24 void SAADC_IRQHandler ();
25 void TIMER0_IRQHandler ();
26 void TIMER1_IRQHandler ();
27 void TIMER2_IRQHandler ();
28 void RTC0_IRQHandler ();
29 void TEMP_IRQHandler ();
30 void RNG_IRQHandler ();
31 void ECB_IRQHandler ();
32 void CCM_AAR_IRQHandler ();
33 void WDT_IRQHandler ();
34 void RTC1_IRQHandler ();
35 void QDEC_IRQHandler ();
36 void COMP_LPCOMP_IRQHandler ();
37 void SWI0_EGU0_IRQHandler ();
38 void SWI1_EGU1_IRQHandler ();
39 void SWI2_EGU2_IRQHandler ();
40 void SWI3_EGU3_IRQHandler ();
41 void SWI4_EGU4_IRQHandler ();
42 void SWI5_EGU5_IRQHandler ();
43 void TIMER3_IRQHandler ();
44 void TIMER4_IRQHandler ();
45 void PWM0_IRQHandler ();
46 void PDM_IRQHandler ();
47 void MWU_IRQHandler ();
48 void PWM1_IRQHandler ();
49 void PWM2_IRQHandler ();
50 void SPIM2_SPIS2_SPI2_IRQHandler ();
51 void RTC2_IRQHandler ();
52 void I2S_IRQHandler ();
53 void FPU_IRQHandler ();
54 void USBD_IRQHandler ();
55 void UARTE1_IRQHandler ();
56 void QSPI_IRQHandler ();
57 void CRYPTOCELL_IRQHandler ();
58 void PWM3_IRQHandler ();
59 void SPIM3_IRQHandler ();
60 }
63 namespace nrfcxx {
64 namespace nrf5 {
65 
66 using FICR_Type = peripheral<NRF_FICR_Type>;
67 static constexpr FICR_Type FICR{NRF_FICR_BASE};
68 
69 using UICR_Type = peripheral<NRF_UICR_Type>;
70 static constexpr UICR_Type UICR{NRF_UICR_BASE};
71 
72 using CLOCK_Type = peripheral<NRF_CLOCK_Type>;
73 static constexpr CLOCK_Type CLOCK{NRF_CLOCK_BASE, POWER_CLOCK_IRQn};
74 
75 using POWER_Type = peripheral<NRF_POWER_Type>;
76 static constexpr POWER_Type POWER{NRF_POWER_BASE, POWER_CLOCK_IRQn};
77 
78 using RADIO_Type = peripheral<NRF_RADIO_Type>;
79 static constexpr RADIO_Type RADIO{NRF_RADIO_BASE, RADIO_IRQn};
80 
81 using UARTE_Type = peripheral<NRF_UARTE_Type>;
82 static constexpr UARTE_Type UARTE0{NRF_UARTE0_BASE, UARTE0_UART0_IRQn, 0};
83 static constexpr UARTE_Type UARTE1{NRF_UARTE1_BASE, UARTE1_IRQn, 1};
84 
85 using UART_Type = peripheral<NRF_UART_Type>;
86 static constexpr UART_Type UART0{NRF_UART0_BASE, UARTE0_UART0_IRQn};
87 
88 using SPIM_Type = peripheral<NRF_SPIM_Type>;
89 static constexpr SPIM_Type SPIM0{NRF_SPIM0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
90 static constexpr SPIM_Type SPIM1{NRF_SPIM1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
91 static constexpr SPIM_Type SPIM2{NRF_SPIM2_BASE, SPIM2_SPIS2_SPI2_IRQn, 2};
92 static constexpr SPIM_Type SPIM3{NRF_SPIM3_BASE, SPIM3_IRQn, 3};
93 
94 using SPIS_Type = peripheral<NRF_SPIS_Type>;
95 static constexpr SPIS_Type SPIS0{NRF_SPIS0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
96 static constexpr SPIS_Type SPIS1{NRF_SPIS1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
97 static constexpr SPIS_Type SPIS2{NRF_SPIS2_BASE, SPIM2_SPIS2_SPI2_IRQn, 2};
98 
99 using SPI_Type = peripheral<NRF_SPI_Type>;
100 static constexpr SPI_Type SPI0{NRF_SPI0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
101 static constexpr SPI_Type SPI1{NRF_SPI1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
102 static constexpr SPI_Type SPI2{NRF_SPI2_BASE, SPIM2_SPIS2_SPI2_IRQn, 2};
103 
104 using TWIM_Type = peripheral<NRF_TWIM_Type>;
105 static constexpr TWIM_Type TWIM0{NRF_TWIM0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
106 static constexpr TWIM_Type TWIM1{NRF_TWIM1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
107 
108 using TWIS_Type = peripheral<NRF_TWIS_Type>;
109 static constexpr TWIS_Type TWIS0{NRF_TWIS0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
110 static constexpr TWIS_Type TWIS1{NRF_TWIS1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
111 
112 using TWI_Type = peripheral<NRF_TWI_Type>;
113 static constexpr TWI_Type TWI0{NRF_TWI0_BASE, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, 0};
114 static constexpr TWI_Type TWI1{NRF_TWI1_BASE, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn, 1};
115 
116 using NFCT_Type = peripheral<NRF_NFCT_Type>;
117 static constexpr NFCT_Type NFCT{NRF_NFCT_BASE, NFCT_IRQn};
118 
119 using GPIOTE_Type = peripheral<NRF_GPIOTE_Type>;
120 static constexpr GPIOTE_Type GPIOTE{NRF_GPIOTE_BASE, GPIOTE_IRQn, GPIOTE_Type::NO_INSTANCE, 8};
121 
122 using SAADC_Type = peripheral<NRF_SAADC_Type>;
123 static constexpr SAADC_Type SAADC{NRF_SAADC_BASE, SAADC_IRQn, SAADC_Type::NO_INSTANCE, 8};
124 static constexpr auto& ADCVariant = SAADC;
125 #define ADCSeriesVariant_IRQHandler SAADC_IRQHandler
126 
127 using TIMER_Type = peripheral<NRF_TIMER_Type>;
128 static constexpr TIMER_Type TIMER0{NRF_TIMER0_BASE, TIMER0_IRQn, 0, 4};
129 static constexpr TIMER_Type TIMER1{NRF_TIMER1_BASE, TIMER1_IRQn, 1, 4};
130 static constexpr TIMER_Type TIMER2{NRF_TIMER2_BASE, TIMER2_IRQn, 2, 4};
131 static constexpr TIMER_Type TIMER3{NRF_TIMER3_BASE, TIMER3_IRQn, 3, 6};
132 static constexpr TIMER_Type TIMER4{NRF_TIMER4_BASE, TIMER4_IRQn, 4, 6};
133 
134 using RTC_Type = peripheral<NRF_RTC_Type>;
135 static constexpr RTC_Type RTC0{NRF_RTC0_BASE, RTC0_IRQn, 0, 3};
136 static constexpr RTC_Type RTC1{NRF_RTC1_BASE, RTC1_IRQn, 1, 4};
137 static constexpr RTC_Type RTC2{NRF_RTC2_BASE, RTC2_IRQn, 2, 4};
138 #define UPTIME_RTC_IRQHandler RTC1_IRQHandler
139 static constexpr const RTC_Type& UPTIME_RTC{RTC1};
140 
141 using TEMP_Type = peripheral<NRF_TEMP_Type>;
142 static constexpr TEMP_Type TEMP{NRF_TEMP_BASE, TEMP_IRQn};
143 
144 using RNG_Type = peripheral<NRF_RNG_Type>;
145 static constexpr RNG_Type RNG{NRF_RNG_BASE, RNG_IRQn};
146 
147 using ECB_Type = peripheral<NRF_ECB_Type>;
148 static constexpr ECB_Type ECB{NRF_ECB_BASE, ECB_IRQn};
149 
150 using CCM_Type = peripheral<NRF_CCM_Type>;
151 static constexpr CCM_Type CCM{NRF_CCM_BASE, CCM_AAR_IRQn};
152 
153 using AAR_Type = peripheral<NRF_AAR_Type>;
154 static constexpr AAR_Type AAR{NRF_AAR_BASE, CCM_AAR_IRQn};
155 
156 using WDT_Type = peripheral<NRF_WDT_Type>;
157 static constexpr WDT_Type WDT{NRF_WDT_BASE, WDT_IRQn};
158 
159 using QDEC_Type = peripheral<NRF_QDEC_Type>;
160 static constexpr QDEC_Type QDEC{NRF_QDEC_BASE, QDEC_IRQn};
161 
162 using COMP_Type = peripheral<NRF_COMP_Type>;
163 static constexpr COMP_Type COMP{NRF_COMP_BASE, COMP_LPCOMP_IRQn};
164 
165 using LPCOMP_Type = peripheral<NRF_LPCOMP_Type>;
166 static constexpr LPCOMP_Type LPCOMP{NRF_LPCOMP_BASE, COMP_LPCOMP_IRQn};
167 
168 using SWI_Type = peripheral<NRF_SWI_Type>;
169 static constexpr SWI_Type SWI0{NRF_SWI0_BASE, SWI0_EGU0_IRQn, 0};
170 static constexpr SWI_Type SWI1{NRF_SWI1_BASE, SWI1_EGU1_IRQn, 1};
171 static constexpr SWI_Type SWI2{NRF_SWI2_BASE, SWI2_EGU2_IRQn, 2};
172 static constexpr SWI_Type SWI3{NRF_SWI3_BASE, SWI3_EGU3_IRQn, 3};
173 static constexpr SWI_Type SWI4{NRF_SWI4_BASE, SWI4_EGU4_IRQn, 4};
174 static constexpr SWI_Type SWI5{NRF_SWI5_BASE, SWI5_EGU5_IRQn, 5};
175 
176 using EGU_Type = peripheral<NRF_EGU_Type>;
177 static constexpr EGU_Type EGU0{NRF_EGU0_BASE, SWI0_EGU0_IRQn, 0};
178 static constexpr EGU_Type EGU1{NRF_EGU1_BASE, SWI1_EGU1_IRQn, 1};
179 static constexpr EGU_Type EGU2{NRF_EGU2_BASE, SWI2_EGU2_IRQn, 2};
180 static constexpr EGU_Type EGU3{NRF_EGU3_BASE, SWI3_EGU3_IRQn, 3};
181 static constexpr EGU_Type EGU4{NRF_EGU4_BASE, SWI4_EGU4_IRQn, 4};
182 static constexpr EGU_Type EGU5{NRF_EGU5_BASE, SWI5_EGU5_IRQn, 5};
183 
184 using PWM_Type = peripheral<NRF_PWM_Type>;
185 static constexpr PWM_Type PWM0{NRF_PWM0_BASE, PWM0_IRQn, 0};
186 static constexpr PWM_Type PWM1{NRF_PWM1_BASE, PWM1_IRQn, 1};
187 static constexpr PWM_Type PWM2{NRF_PWM2_BASE, PWM2_IRQn, 2};
188 static constexpr PWM_Type PWM3{NRF_PWM3_BASE, PWM3_IRQn, 3};
189 
190 using PDM_Type = peripheral<NRF_PDM_Type>;
191 static constexpr PDM_Type PDM0{NRF_PDM_BASE, PDM_IRQn};
192 
193 using NVMC_Type = peripheral<NRF_NVMC_Type>;
194 static constexpr NVMC_Type NVMC{NRF_NVMC_BASE};
195 
196 struct PPI_Type : public peripheral<NRF_PPI_Type>
197 {
201  static constexpr size_t NUM_CHANNELS = 20;
202 
204  using channel_set_type = uint32_t;
205 
207  static constexpr size_t NUM_GROUPS = 4;
208 
210  using group_set_type = uint8_t;
211 
212  constexpr PPI_Type () :
213  peripheral<NRF_PPI_Type>{NRF_PPI_BASE, PPI_Type::NO_IRQ, PPI_Type::NO_INSTANCE, NUM_CHANNELS}
214  { }
215 };
216 static constexpr PPI_Type PPI{};
217 
218 using MWU_Type = peripheral<NRF_MWU_Type>;
219 static constexpr MWU_Type MWU{NRF_MWU_BASE, MWU_IRQn};
220 
221 using I2S_Type = peripheral<NRF_I2S_Type>;
222 static constexpr I2S_Type I2S{NRF_I2S_BASE, I2S_IRQn};
223 
224 using USBD_Type = peripheral<NRF_USBD_Type>;
225 static constexpr USBD_Type USBD{NRF_USBD_BASE, USBD_IRQn};
226 
227 using QSPI_Type = peripheral<NRF_QSPI_Type>;
228 static constexpr QSPI_Type QSPI{NRF_QSPI_BASE, QSPI_IRQn};
229 
230 using CC_HOST_RGF_Type = peripheral<NRF_CC_HOST_RGF_Type>;
231 static constexpr CC_HOST_RGF_Type CC_HOST_RGF{NRF_CC_HOST_RGF_BASE};
232 
233 using CRYPTOCELL_Type = peripheral<NRF_CRYPTOCELL_Type>;
234 static constexpr CRYPTOCELL_Type CRYPTOCELL{NRF_CRYPTOCELL_BASE, CRYPTOCELL_IRQn};
235 
236 #if 0
237 /* Nordic defines their macro as FPU instead of NRF_FPU */
238 using FPU_Type = peripheral<NRF_FPU_Type>;
239 static constexpr FPU_Type FPU{NRF_FPU_BASE, FPU_IRQn};
240 #endif
241 
242 using GPIO_Type = peripheral<NRF_GPIO_Type>;
243 static constexpr GPIO_Type P0{NRF_P0_BASE, GPIO_Type::NO_IRQ, 0, 32};
244 static constexpr GPIO_Type P1{NRF_P1_BASE, GPIO_Type::NO_IRQ, 1, 16};
245 static constexpr int GPIO_PSEL_COUNT = 48;
246 static constexpr const GPIO_Type& GPIO{P0};
247 
248 template <>
249 struct GPIO_Instance<0>
250 {
251  static constexpr const GPIO_Type& peripheral{P0};
252  static constexpr int begin_psel = 0;
253  static constexpr int end_psel = begin_psel + P0.AUX;
254 };
255 
256 template <>
257 struct GPIO_Instance<1> {
258  static constexpr const GPIO_Type& peripheral{P1};
259  static constexpr int begin_psel = GPIO_Instance<0>::end_psel;
260  static constexpr int end_psel = begin_psel + P1.AUX;
261 };
262 
263 } // ns nrf5
264 } // ns nrfcxx
265 
266 #endif /* NRFCXX_NRF52840_HPP */
nrfcxx::nrf5::PPI_Type
Definition: core.hpp:147
nrfcxx::nrf5::peripheral< NRF_PPI_Type >::NO_IRQ
static constexpr int8_t NO_IRQ
Flag value for IRQn indicating that the peripheral does not have an assign interrupt vector entry.
Definition: core.hpp:172
nrfcxx::nrf5::GPIO_PSEL_COUNT
static constexpr int GPIO_PSEL_COUNT
The number of GPIO PSEL ordinals supported by the platform.
Definition: core.hpp:178
nrfcxx::nrf5::peripheral
Capture information about an nRF5 peripheral instance.
Definition: core.hpp:165
nrfcxx::nrf5::peripheral::AUX
const uint8_t AUX
Auxiliary information relevant to the specific peripheral and type.
Definition: core.hpp:245
nrfcxx::nrf5::GPIO_Instance
A traits type identifying GPIO peripheral instances.
Definition: core.hpp:260
nrfcxx::nrf5::PPI_Type::NUM_GROUPS
static constexpr size_t NUM_GROUPS
The number of channel groups.
Definition: core.hpp:157
nrfcxx::nrf5::PPI_Type::NUM_CHANNELS
static constexpr size_t NUM_CHANNELS
The number of configurable channels.
Definition: core.hpp:151
nrfcxx::nrf5::PPI_Type::group_set_type
uint8_t group_set_type
Bit-mask type to record sets of configurable channels.
Definition: core.hpp:160
nrfcxx::nrf5::peripheral::NO_INSTANCE
static constexpr uint8_t NO_INSTANCE
Flag value for INSTANCE indicating that the peripheral does not have enumerated instances (e....
Definition: core.hpp:177
nrfcxx::nrf5::PPI_Type::channel_set_type
uint16_t channel_set_type
Bit-mask type to record sets of configurable channels.
Definition: core.hpp:154
nrfcxx
Primary namespace for nrfcxx functionality.
Definition: clock.hpp:17
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