impl.hpp

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/* SPDX-License-Identifier: Apache-2.0 */
/* Copyright 2018-2019 Peter A. Bigot */
 
#ifndef NRFCXX_NRF52_IMPL_HPP
#define NRFCXX_NRF52_IMPL_HPP
#pragma once
 
#if (NRF52832 - 0)
#include <nrf52_bitfields.h>
#elif (NRF52840 - 0)
#include <nrf52840_bitfields.h>
#else /* TARGET_PRODUCT */
#error Unsupported NRF52 MCU
#endif /* NRF52 */
 
namespace nrfcxx {
namespace nrf5 {
namespace series {
 
struct SAADC_Peripheral : public ADC_Base {
  using mutex_type = mutex_irq<static_cast<IRQn_Type>(nrf5::SAADC.IRQn)>;
 
  static constexpr IRQn_Type IRQn = SAADC_IRQn;
 
  static constexpr unsigned int VBG_mV = 600;
 
  static constexpr uint16_t TOLERANCE_adc16 = (1U << 7);
 
  static constexpr bool near_zero (uint16_t v_adc16)
  {
    return ((TOLERANCE_adc16 > v_adc16)
            || (v_adc16 >= ((1U << 16) - TOLERANCE_adc16)));
  }
 
  static constexpr
  unsigned int
  make_config (unsigned int refsel = SAADC_CH_CONFIG_REFSEL_Internal,
               unsigned int gain = SAADC_CH_CONFIG_GAIN_Gain1_6,
               unsigned int tacq = SAADC_CH_CONFIG_TACQ_10us,
               bool burst = true,
               unsigned int resp = SAADC_CH_CONFIG_RESP_Bypass,
               bool differential = false,
               unsigned int resn = SAADC_CH_CONFIG_RESN_Bypass)
  {
    return 0
      | (SAADC_CH_CONFIG_RESP_Msk & (resp << SAADC_CH_CONFIG_RESP_Pos))
      | (SAADC_CH_CONFIG_RESN_Msk & (resn << SAADC_CH_CONFIG_RESN_Pos))
      | (SAADC_CH_CONFIG_GAIN_Msk & (gain << SAADC_CH_CONFIG_GAIN_Pos))
      | (SAADC_CH_CONFIG_REFSEL_Msk & (refsel << SAADC_CH_CONFIG_REFSEL_Pos))
      | (SAADC_CH_CONFIG_TACQ_Msk & (tacq << SAADC_CH_CONFIG_TACQ_Pos))
      | (SAADC_CH_CONFIG_MODE_Msk & (differential << SAADC_CH_CONFIG_MODE_Pos))
      | (SAADC_CH_CONFIG_BURST_Msk & (burst << SAADC_CH_CONFIG_BURST_Pos));
  }
 
  static constexpr uint32_t inten = 0
    | (SAADC_INTENSET_CALIBRATEDONE_Set << SAADC_INTENSET_CALIBRATEDONE_Pos)
    | (SAADC_INTENSET_STARTED_Set << SAADC_INTENSET_STARTED_Pos)
    | (SAADC_INTENSET_DONE_Set << SAADC_INTENSET_DONE_Pos)
    | (SAADC_INTENSET_RESULTDONE_Set << SAADC_INTENSET_RESULTDONE_Pos)
    | (SAADC_INTENSET_END_Set << SAADC_INTENSET_END_Pos)
    | (SAADC_INTENSET_STOPPED_Set << SAADC_INTENSET_STOPPED_Pos);
 
  static bool busy ()
  {
    return nrf5::SAADC->STATUS;
  }
 
  /* PAN 74: SAADC: Started events fires prematurely.
   * If TACQ <= 5 us EVENTS_STARTED may be spontaneously generated after ENABLE.
   * (Workaround does not work)
   *
   * PAN 86: SAADC: Triggering START after calibration may write sample to RAM
   * After CALIBRATEDONE issue STOP and wait for STOPPED before issuing START.
   *
   * PAN 150: SAADC: EVENT_STARTED does not fire
   * Applies to PPI-initiated START with TACQ <= 5 us
   *
   * PAN 178: SAADC: END event firing too early
   * END event occurs before data ready when CALIBRATE with TACQ < 10us before SAMPLE.
   *
   * Observations:
   *
   * With TACQ <= 5 us CALIBRATE without START generates:
   * * DONE which remains asserted for 4.252 us (with TACQ 3 us)
   * * anomalous STARTED 5 us after DONE asserted (PAN 74)
   * * two more DONE events
   * * CALIBRATEDONE 64 ns after the third DONE deasserts
   * * anomalous DONE 4.248 us after CALIBRATEDONE
   *
   * With TACQ = 40 us CALIBRATE without START generates:
   * * DONE which remains asserted for 41.252 us
   * * two more DONE events
   * * CALIBRATEDONE 104 ns after third DONE deasserts
   * * anomalous DONE 41.144 us after CALIBRATEDONE
   *
   * The extra DONE event may be the fault underlying PAN 86.  If STOP
   * is issued quickly enough the extra DONE event does not happen.
   *
   * With TACQ <= 5 us START, [DONE], STARTED, CALIBRATE produces END
   * This is consistent with PAN 178.
   *
   * With TACQ = 40 us START, STARTED, CALIBRATE produces END before CALIBRATEDONE
   * This is consistent with PAN 178 except observed with long TACQ.
   *
   * Without ENABLE issuing START produces STARTED.  Issuing SAMPLE or
   * CALIBRATE has no effect.
   *
   * Workarounds:
   * * Issue CALIBRATE after ENABLE before START.
   * * Issue STOP after CALIBRATE_DONE and wait for STOPPED
   * * Ignore STARTED except after explicit START.
   */
 
  static void enable_bi ()
  {
    nrf5::SAADC->EVENTS_STARTED = 0;
    nrf5::SAADC->EVENTS_END = 0;
    nrf5::SAADC->EVENTS_DONE = 0;
    nrf5::SAADC->EVENTS_STOPPED = 0;
    nrf5::SAADC->EVENTS_CALIBRATEDONE = 0;
    nrf5::SAADC->RESULT.PTR = reinterpret_cast<uint32_t>(result_ptr_);
    nrf5::SAADC->RESULT.MAXCNT = result_maxcnt_;
    nrf5::SAADC->INTENSET = inten;
    nvic_ClearPendingIRQ(IRQn);
    nvic_EnableIRQ(IRQn);
    nrf5::SAADC->ENABLE = 1;
  }
 
  static bool calibrating_bi_;
 
  static void disable_bi ()
  {
    nrf5::SAADC->ENABLE = 0;
    nvic_DisableIRQ(IRQn);
    nrf5::SAADC->INTENCLR = inten;
  }
 
  static int calibrate_bi ()
  {
    enable_bi();
    calibrating_bi_ = true;
    nrf5::SAADC->TASKS_CALIBRATEOFFSET = 1;
    return 1;
  }
 
  static int start_bi ()
  {
    enable_bi();
    calibrating_bi_ = false;
    nrf5::SAADC->TASKS_START = 1;
    return 1;
  }
 
  static void stopped_bi ()
  {
    disable_bi();
  }
 
  static unsigned int normalize_bi ()
  {
    volatile uint16_t* rp = result_ptr_;
    volatile uint16_t* const rpe = rp + result_maxcnt_;
 
    // NB: RESOLUTION is a 7-bit value, but only the low two bits
    // are defined to be supported.  If we used
    // SAADC_RESOLUTION_VAL_Msk we could end up with a negative
    // shift.
    unsigned int shift16 = 8 - 2 * ((nrf5::SAADC->RESOLUTION & 0x03) >> SAADC_RESOLUTION_VAL_Pos);
    while (rp < rpe) {
      *rp++ <<= shift16;
    }
    return *result_ptr_;
  }
};
 
using ADC_Variant = SAADC_Peripheral;
 
} // ns series
} // ns nrf5
 
 
static constexpr auto IRQ_PRIORITY_SD_HIGH = 0;
 
static constexpr auto IRQ_PRIORITY_SD_MEMORY = 1;
 
static constexpr auto IRQ_PRIORITY_APP_HIGH = 2;
 
static constexpr auto IRQ_PRIORITY_SD_LOW = 4;
 
static constexpr auto IRQ_PRIORITY_APP_LOW = 5;
 
} // ns nrfcxx
 
#endif /* NRFCXX_NRF52_IMPL_HPP */