device.h

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/* Copyright 2014, Peter A. Bigot
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * * Neither the name of the software nor the names of its contributors may be
 *   used to endorse or promote products derived from this software without
 *   specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef BSPACM_DEVICE_EFM32_H
#define BSPACM_DEVICE_EFM32_H

#if ! (BSPACM_DEVICE_SERIES_EFM32 - 0)
#error EFM32 device header in non-EFM32 device
#endif /* BSPACM_DEVICE_SERIES_EFM32 */

#include <em_device.h>
#include <em_emu.h>

void vBSPACMdeviceEFM32setupSWO(void);

#define BSPACM_CORE_SLEEP() do { \
    EMU_EnterEM1();              \
  } while(0)

#define BSPACM_CORE_DEEP_SLEEP() do {   \
    EMU_EnterEM2(true);                 \
    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; \
  } while(0)

/* @cond DOXYGEN_EXCLUDE */
/* SRAM and peripheral bitband addresses are in standard Cortex-M3/M4
 * locations for everything except the Cortex-M0+ Zero Gecko line. */
#if ! (_EFM32_ZERO_FAMILY - 0)
#define BSPACM_CORE_SRAM_BASE ((uintptr_t)0x20000000)
#define BSPACM_CORE_SRAM_BITBAND_BASE ((uintptr_t)0x22000000)
#define BSPACM_CORE_PERIPH_BASE ((uintptr_t)0x40000000)
#define BSPACM_CORE_PERIPH_BITBAND_BASE ((uintptr_t)0x42000000)
#endif /* ! Zero Gecko */
/* @endcond */

#endif /* BSPACM_DEVICE_EFM32_H */